Mario Drumond

Orcid: 0000-0002-1981-3525

According to our database1, Mario Drumond authored at least 16 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Scale-out Systolic Arrays.
ACM Trans. Archit. Code Optim., June, 2023

2021
Efficient Nearest-Neighbor Data Sharing in GPUs.
ACM Trans. Archit. Code Optim., 2021

Equinox: Training (for Free) on a Custom Inference Accelerator.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
ColTraIn: Co-located DNN training and inference.
PhD thesis, 2020

Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.
CoRR, 2020

Optimus Prime: Accelerating Data Transformation in Servers.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Highly Concurrent Latency-tolerant Register Files for GPUs.
ACM Trans. Comput. Syst., 2019

Analog Neural Networks With Deep-Submicrometer Nonlinear Synapses.
IEEE Micro, 2019

2018
Algorithm/Architecture Co-Design for Near-Memory Processing.
ACM SIGOPS Oper. Syst. Rev., 2018

End-to-End DNN Training with Block Floating Point Arithmetic.
CoRR, 2018

Training DNNs with Hybrid Block Floating Point.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
The Mondrian Data Engine.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2015
Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU.
ACM Trans. Archit. Code Optim., 2015

MIAOW: An open source GPGPU.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

MIAOW - An open source RTL implementation of a GPGPU.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015


  Loading...