Rachata Ausavarungnirun

Orcid: 0000-0002-1459-0852

Affiliations:
  • King Mongkut's University of Technology North Bangkok, Thailand
  • Carnegie Mellon University (former)


According to our database1, Rachata Ausavarungnirun authored at least 72 papers between 2012 and 2024.

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Timeline

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Bibliography

2024
More Apps, Faster Hot-Launch on Mobile Devices via Fore/Background-aware GC-Swap Co-design.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

ICE: Collaborating Memory and Process Management for User Experience on Resource-limited Mobile Devices.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023

vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Utopia: Efficient Address Translation using Hybrid Virtual-to-Physical Address Mapping.
CoRR, 2022

RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory.
CoRR, 2022

GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis.
CoRR, 2022

Chapter Eight - The design of an energy-efficient deflection-based on-chip network.
Adv. Comput., 2022

Memory Harvesting in Multi-GPU Systems with Hierarchical Unified Virtual Memory.
Proceedings of the 2022 USENIX Annual Technical Conference, 2022

GenStore: In-Storage Filtering of Genomic Data for High-Performance and Energy-Efficient Genome Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

CacheSifter: Sifting Cache Files for Boosted Mobile Performance and Lifetime.
Proceedings of the 20th USENIX Conference on File and Storage Technologies, 2022

GenStore: a high-performance in-storage processing system for genome sequence analysis.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control.
CoRR, 2021

SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems.
CoRR, 2021

SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

FPRA: A Fine-grained Parallel RRAM Architecture.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
A Modern Primer on Processing in Memory.
CoRR, 2020

Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.
CoRR, 2020

NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories.
IEEE Comput. Archit. Lett., 2020

Acclaim: Adaptive Memory Reclaim to Improve User Experience in Android Systems.
Proceedings of the 2020 USENIX Annual Technical Conference, 2020

GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Differentiating Cache Files for Fine-grain Management to Improve Mobile Performance and Lifetime.
Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

PRISM: Architectural Support for Variable-granularity Memory Metadata.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Highly Concurrent Latency-tolerant Register Files for GPUs.
ACM Trans. Comput. Syst., 2019

ITAP: Idle-Time-Aware Power Management for GPU Execution Units.
ACM Trans. Archit. Code Optim., 2019

Processing data where it makes sense: Enabling in-memory computation.
Microprocess. Microsystems, 2019

Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

CoNDA: efficient cache coherence support for near-data accelerators.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Enabling Practical Processing in and near Memory for Data-Intensive Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors.
ACM SIGOPS Oper. Syst. Rev., 2018

Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results.
CoRR, 2018

Recent Advances in DRAM and Flash Memory Architectures.
CoRR, 2018

Recent Advances in Overcoming Bottlenecks in Memory Systems and Managing Memory Resources in GPU Systems.
CoRR, 2018

RowClone: Accelerating Data Movement and Initialization Using DRAM.
CoRR, 2018

Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs.
CoRR, 2018

High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems.
CoRR, 2018

A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems.
CoRR, 2018

Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance.
CoRR, 2018

Techniques for Shared Resource Management in Systems with Throughput Processors.
CoRR, 2018

Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions.
CoRR, 2018

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Techniques for Shared Resource Management in Systems with Throughput Processors.
PhD thesis, 2017

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
Proc. ACM Meas. Anal. Comput. Syst., 2017

Improving Multi-Application Concurrency Support Within the GPU Memory System.
CoRR, 2017

Mosaic: a GPU memory manager with application-transparent support for multiple page sizes.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate.
Parallel Comput., 2016

A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps.
CoRR, 2016

Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
CoRR, 2016

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing.
CoRR, 2016

SizeCap: Efficiently handling power surges in fuel cell powered data centers.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

μC-States: Fine-grained GPU Datapath Power Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

A case for core-assisted bottleneck acceleration in GPUs: enabling flexible data compression with assist warps.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Design and Evaluation of Hierarchical Rings with Deflection Routing.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Managing GPU Concurrency in Heterogeneous Architectures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Application-to-core mapping policies to reduce memory system interference in multi-core systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Row buffer locality aware caching policies for hybrid memories.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Application-to-core mapping policies to reduce memory interference in multi-core systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012


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