Boris Grot

Orcid: 0000-0001-6525-0762

Affiliations:
  • University of Edinburgh, UK


According to our database1, Boris Grot authored at least 66 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2023
Expedited Data Transfers for Serverless Clouds.
CoRR, 2023

Enabling In-Vitro Serverless Systems Research.
Proceedings of the 4th Workshop on Resource Disaggregation and Serverless, 2023

Warming Up a Cold Front-End with Ignite.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Concurrent GCs and Modern Java Workloads: A Cache Perspective.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

A Storage-Effective BTB Organization for Servers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Saba: Rethinking Datacenter Network Allocation from Application's Perspective.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023

2022
Reconsidering OS memory optimizations in the presence of disaggregated memory.
Proceedings of the ISMM '22: ACM SIGPLAN International Symposium on Memory Management, 2022

Lukewarm serverless functions: characterization and optimization.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

A Specialized BTB Organization for Servers.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Branch Prediction as a Reinforcement Learning Problem: Why, How and Case Studies.
CoRR, 2021

BTB-X: A Storage-Effective BTB Organization.
IEEE Comput. Archit. Lett., 2021

Morrigan: A Composite Instruction TLB Prefetcher.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Analyzing Tail Latency in Serverless Clouds with STeLLAR.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

Zeus: locality-aware distributed transactions.
Proceedings of the EuroSys '21: Sixteenth European Conference on Computer Systems, 2021

Benchmarking, analysis, and optimization of serverless function snapshots.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Shooting Down the Server Front-End Bottleneck.
ACM Trans. Comput. Syst., 2020

Fetch-Directed Instruction Prefetching Revisited.
CoRR, 2020

Bankrupt Covert Channel: Turning Network Predictability into Vulnerability.
Proceedings of the 14th USENIX Workshop on Offensive Technologies, 2020

Kite: efficient and available release consistency for the datacenter.
Proceedings of the PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020

Evaluation of an InfiniBand Switch: Choose Latency or Bandwidth, but Not Both.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

Domain-Specialized Cache Management for Graph Analytics.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Population-based evolutionary distributed SGD.
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020

Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Prefetched Address Translation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Closer Look at Lightweight Graph Reordering.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

POSTER: Domain-Specialized Cache Management for Graph Analytics.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling.
ACM Trans. Comput. Syst., 2018

Algorithm/Architecture Co-Design for Near-Memory Processing.
ACM SIGOPS Oper. Syst. Rev., 2018

Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Scale-out ccNUMA: exploiting skew with strongly consistent caching.
Proceedings of the Thirteenth EuroSys Conference, 2018

Blasting through the Front-End Bottleneck with Shotgun.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Fat Caches for Scale-Out Servers.
IEEE Micro, 2017

The Mondrian Data Engine.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Boomerang: A Metadata-Free Architecture for Control Flow Delivery.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Near-Data Processing [Guest editors' introduction].
IEEE Micro, 2016

An Analysis of Load Imbalance in Scale-out Data Serving.
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016

C<sup>3</sup>D: Mitigating the NUMA bottleneck via coherent DRAM caches.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

SABRes: Atomic object reads for in-memory rack-scale computing.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

The Case for RackOut: Scalable Data Serving Using Rack-Scale Systems.
Proceedings of the Seventh ACM Symposium on Cloud Computing, 2016

2015
Asynchronous Memory Access Chaining.
Proc. VLDB Endow., 2015

Confluence: unified instruction supply for scale-out servers.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Manycore network interfaces for in-memory rack-scale computing.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.
IEEE Trans. Computers, 2014

Big Data [Guest editors' introduction].
IEEE Micro, 2014

BuMP: Bulk Memory Access Prediction and Streaming.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

FADE: A programmable filtering accelerator for instruction-grain monitoring.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Scale-out NUMA.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Meet the walkers: accelerating index traversals for in-memory databases.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

SHIFT: shared history instruction fetch for lean-core server processors.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Optimizing Data-Center TCO with Scale-Out Processors.
IEEE Micro, 2012

A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips.
IEEE Micro, 2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

NOC-Out: Microarchitecting a Scale-Out Processor.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Scale-out processors.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
Reducing network-on-chip energy consumption through spatial locality speculation.
Proceedings of the NOCS 2011, 2011

Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
Netrace: dependency-driven trace-based network-on-chip simulation.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors.
Proceedings of the Computer Architecture, 2010

2009
Segment gating for static energy reduction in Networks-on-Chip.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Express Cube Topologies for on-Chip Interconnects.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Regional congestion awareness for load balance in networks-on-chip.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008


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