Mario Steinert

According to our database1, Mario Steinert authored at least 5 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Power reduction of ASIPs by distributing the workload on several ASIP-instances.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A power dissipation comparison of ALU-architectures for ASIPs.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Power consumption optimization for low latency Viterbi Decoder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

RTL Processor Synthesis for Architecture Exploration and Implementation.
Proceedings of the 2004 Design, 2004

2002
Testability of path history memories with register-exchange architecture used in Viterbi-decoders.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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