Heinrich Meyr
Affiliations:- RWTH Aachen University, Germany
According to our database1,
Heinrich Meyr
authored at least 218 papers
between 1975 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1986, "For contributions to the theory of tracking loops and synchronization.".
Timeline
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Bibliography
2020
Observability Analysis of Flight State Estimation for UAVs and Experimental Validation.
Proceedings of the 2020 IEEE International Conference on Robotics and Automation, 2020
2018
2017
On the Performance Gap Between ML and Iterative Decoding of Finite-Length Turbo-Coded BICM in MIMO Systems.
IEEE Trans. Commun., 2017
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017
2015
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015
2014
IEEE Trans. Inf. Theory, 2014
2013
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels With Gaussian Inputs.
IEEE Trans. Inf. Theory, 2013
2012
On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels.
IEEE Trans. Inf. Theory, 2012
IEEE Trans. Commun., 2012
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Searching for optimal scheduling of MIMO doubly iterative receivers: An ant colony optimization-based method.
Proceedings of the 2012 IEEE Global Communications Conference, 2012
A 2.78 mm<sup>2</sup> 65 nm CMOS gigabit MIMO iterative detection and decoding receiver.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE Trans. Wirel. Commun., 2011
IEEE Trans. Commun., 2011
Des. Autom. Embed. Syst., 2011
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels with Gaussian Inputs
CoRR, 2011
Achievable rate with receivers using iterative channel estimation in stationary fading channels.
Proceedings of the 8th International Symposium on Wireless Communication Systems, 2011
Proceedings of IEEE International Conference on Communications, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE Trans. Commun., 2010
IEEE Trans. Commun., 2010
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Int. J. Parallel Program., 2010
Int. J. Embed. Real Time Commun. Syst., 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the International Symposium on Information Theory and its Applications, 2010
The achievable rate of stationary rayleigh flat-fading channels with IID input symbols.
Proceedings of the International Symposium on Information Theory and its Applications, 2010
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 44th Annual Conference on Information Sciences and Systems, 2010
2009
ACM Trans. Archit. Code Optim., 2009
Microelectron. J., 2009
IACR Cryptol. ePrint Arch., 2009
CoRR, 2009
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations.
Proceedings of the Third IEEE International Conference on Secure Software Integration and Reliability Improvement, 2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).
Proceedings of the Embedded Computer Systems: Architectures, 2009
Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties.
Proceedings of the IEEE 20th International Symposium on Personal, 2009
Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder.
Proceedings of the IEEE 20th International Symposium on Personal, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
IEEE Trans. Wirel. Commun., 2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embed. Comput. Syst., 2008
J. Comput., 2008
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
Int. J. Embed. Syst., 2008
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
Int. J. Embed. Syst., 2008
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008
Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI.
Proceedings of IEEE International Conference on Communications, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
ACM Trans. Embed. Comput. Syst., 2007
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems.
Proceedings of the Global Communications Conference, 2007
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the 2007 International Conference on Compilers, 2007
Kluwer, ISBN: 978-1-4020-5685-7, 2007
2006
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
J. VLSI Signal Process., 2006
Proceedings of the IEEE 17th International Symposium on Personal, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of IEEE International Conference on Communications, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
An interprocedural code optimization technique for network processors using hardware multi-threading support.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Integrated system-level modeling of network-on-chip enabled multi-processor platforms.
Kluwer, ISBN: 978-1-4020-4825-8, 2006
2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 60th IEEE Vehicular Technology Conference, 2004
Proceedings of the Computer Systems: Architectures, 2004
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
Proceedings of the Computer Systems: Architectures, 2004
Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
Proceedings of IEEE International Conference on Communications, 2004
Performance of initial synchronization schemes for WCDMA systems with spatio-temporal correlations.
Proceedings of IEEE International Conference on Communications, 2004
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IEEE Des. Test Comput., 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the Global Telecommunications Conference, 2003
The effect of imperfect SNR knowledge on multiantenna multiuser systems with channel aware scheduling.
Proceedings of the Global Telecommunications Conference, 2003
Initial synchronization of W-CDMA systems using a power-scaled detector with antenna diversity in frequency-selective Rayleigh fading channels.
Proceedings of the Global Telecommunications Conference, 2003
Proceedings of the 2003 Design, 2003
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
Proceedings of the 40th Design Automation Conference, 2003
A modular simulation framework for architectural exploration of on-chip interconnection networks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
2002
EURASIP J. Adv. Signal Process., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 2002 Joint Conference on Languages, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the IEEE International Conference on Communications, 2002
Architecture exploration for embedded processors with LISA.
Kluwer, ISBN: 978-1-4020-7338-0, 2002
2001
IEEE Trans. Commun., 2001
IEEE Trans. Commun., 2001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE J. Sel. Areas Commun., 2001
Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving.
IEEE J. Sel. Areas Commun., 2001
Proceedings of the 2001 IEEE Information Theory Workshop, 2001
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Generating production quality software development tools using a machine description language.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Retargetable compiled simulation of embedded processors using a machine description language.
ACM Trans. Design Autom. Electr. Syst., 2000
Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language.
Proceedings of the 2000 Design, 2000
Efficient building block based RTL code generation from synchronous data flow graphs.
Proceedings of the 37th Conference on Design Automation, 2000
1999
IEEE Trans. Commun., 1999
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs.
Proceedings of the 12th International Symposium on System Synthesis, 1999
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures.
Proceedings of the 36th Conference on Design Automation, 1999
1998
An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization.
Wirel. Pers. Commun., 1998
Proceedings of the 1998 Design, 1998
Digital communication receivers - synchronization, channel estimation, and signal processing.
Wiley series in telecommunications and signal processing, Wiley, ISBN: 978-0-471-50275-3, 1998
1997
Authors' reply [to "Comment on cycle slips in synchronizers subject to smooth narrow-band loop noise"].
IEEE Trans. Commun., 1997
IEEE Commun. Lett., 1997
Modulo-addressing utilization in automatic software synthesis for digital signal processors.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations.
IEEE Trans. Computers, 1996
Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study.
Des. Autom. Embed. Syst., 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Commun. Mag., 1995
Proceedings of the 6th IEEE International Symposium on Personal, 1995
Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding.
Proceedings of the 6th IEEE International Symposium on Personal, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Scheduling for optimum data memory compaction in block diagram oriented software synthesis.
Proceedings of the 1995 International Conference on Acoustics, 1995
DSP-based mobile and satellite receivers, from algorithm to implementation: a design course at Aachen University of Technology.
Proceedings of the 1995 International Conference on Acoustics, 1995
Proceedings of the 1995 International Conference on Acoustics, 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
J. VLSI Signal Process., 1994
On sampling rate, analog prefiltering, and sufficient statistics for digital receivers.
IEEE Trans. Commun., 1994
Optimal parametric feedforward estimation of frequency-selective fading radio channels.
IEEE Trans. Commun., 1994
A digital feedforward differential detection MSK receiver for packet-based mobile radio.
Proceedings of 44th IEEE Vehicular Technology Conference: Creating Tomorrow's Mobile Systems, 1994
Frequency synchronization algorithms for OFDM systems suitable for communication over frequency selective fading channels.
Proceedings of 44th IEEE Vehicular Technology Conference: Creating Tomorrow's Mobile Systems, 1994
Improved frame synchronization for spontaneous packet transmission over frequency-selective radio channels.
Proceedings of the 5th IEEE International Symposium on Personal, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
1993
IEEE J. Sel. Areas Commun., 1993
Matched Filter Bound for Trellis-Coded Transmission over Frequency-Selective Fading Channels with Diversity.
Eur. Trans. Telecommun., 1993
Design of optimum interpolation filters for digital demodulators.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1992
A new mobile digital radio transceiver concept using low-complexity combined equalization/trellis decoding and a near-optimal receiver sync strategy.
Proceedings of the Third IEEE International Symposium on Personal, 1992
Proceedings of the Application Specific Array Processors, 1992
Proceedings of the Application Specific Array Processors, 1992
1991
J. VLSI Signal Process., 1991
A new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels.
IEEE Trans. Commun., 1991
IEEE Commun. Mag., 1991
1990
On the error probability of linearly modulated signals on Rayleigh frequency-flat fading channels.
IEEE Trans. Commun., 1990
IEEE J. Sel. Areas Commun., 1990
1989
A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels.
IEEE Trans. Commun., 1989
IEEE Trans. Commun., 1989
An all digital receiver architecture for bandwidth efficient transmission at high data rates.
IEEE Trans. Commun., 1989
Adaptive synchronization and channel parameter estimation using an extended Kalman filter.
IEEE Trans. Commun., 1989
1988
IEEE Trans. Acoust. Speech Signal Process., 1988
IEEE Trans. Commun., 1988
Proceedings of the 13th Conference on Local Computer Networks, 1988
1987
A Simple Method for Evaluating the Probability Density Function of the Sample Number for the Optimum Sequential Detector.
IEEE Trans. Commun., 1987
1986
An all-digital realization of a baseband DLL implemented as a dynamical state estimator.
IEEE Trans. Acoust. Speech Signal Process., 1986
1983
IEEE Trans. Commun., 1983
IEEE J. Sel. Areas Commun., 1983
1982
Proceedings of the IEEE International Conference on Acoustics, 1982
1980
1978
Theory of phase tracking systems of arbitrary order: Statistics of cycle slips and probability distribution of the state vector.
IEEE Trans. Inf. Theory, 1978
1977
Complete statistical description of the phase-error process generated by correlative tracking systems.
IEEE Trans. Inf. Theory, 1977
1976
1975
IEEE Trans. Commun., 1975