Aravind Tharayil Narayanan

According to our database1, Aravind Tharayil Narayanan authored at least 26 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
IEEE J. Solid State Circuits, 2020

2019
ULPAC: A Miniaturized Ultralow-Power Atomic Clock.
IEEE J. Solid State Circuits, 2019

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio.
IEEE J. Solid State Circuits, 2019

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock.
IEICE Trans. Electron., 2019

A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM.
IEICE Trans. Electron., 2019

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10<sup>-12</sup> Long-Term Allan Deviation Using Cesium Coherent Population Trapping.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS.
IEICE Trans. Electron., 2018

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI.
IEICE Trans. Electron., 2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016

A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
An AM-PM Noise Mitigation Technique in Class-C VCO.
IEICE Trans. Electron., 2015

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI.
IEICE Electron. Express, 2015

14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015

A tail-current modulated VCO with adaptive-bias scheme.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz.
Proceedings of the ESSCIRC 2014, 2014

A 0.011 mm<sup>2</sup> PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014


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