Kevin J. Nowka

According to our database1, Kevin J. Nowka authored at least 57 papers between 1995 and 2023.

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Bibliography

2023
Realistic Predictors for Regression and Semantic Segmentation.
Proceedings of the 21st IEEE/ACIS International Conference on Software Engineering Research, 2023

A Deep Transfer Learning based approach for forecasting spatio-temporal features to maximize yield in cotton crops.
Proceedings of the 57th Annual Conference on Information Sciences and Systems, 2023

2015
Second-Generation Big Data Systems.
Computer, 2015

2012
Transforming memory systems: Optimizing for client value on emerging workloads.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
On-Chip Delay Measurement Based Response Analysis for Timing Characterization.
J. Electron. Test., 2010

Physical design challenges beyond the 22nm node.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Technology variability and uncertainty implications for power- efficient VLSI systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010


2009
Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Performance-Optimized Design for Parametric Reliability.
J. Electron. Test., 2008

A Design Model for Random Process Variability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.
Proceedings of the ESSCIRC 2008, 2008

Characterization and design for variability and reliability.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Dynamic Power Management by Combination of Dual Static Supply Voltages.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Rigorous extraction of process variations for 65nm CMOS design.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
A Scheme for On-Chip Timing Characterization.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

SRAM Local Bit Line Access Failure Analyses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Power Gating with Multiple Sleep Modes.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A dual-V<sub>DD</sub> boosted pulsed bus technique for low power and low leakage operation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Fine grained multi-threshold CMOS for enhanced leakage reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Adaptive Design for Performance-Optimized Robustness.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Guest Editors' Introduction: New Dimensions in 3D Integration.
IEEE Des. Test Comput., 2005

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Controlled-Load Limited Switch Dynamic Logic Circuit.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Resonant clocking using distributed parasitic capacitance.
IEEE J. Solid State Circuits, 2004

Approaches to run-time and standby mode leakage reduction in global buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Requirement-based design methods for adaptive communications links.
Proceedings of the 41th Design Automation Conference, 2004

2003
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip.
IBM J. Res. Dev., 2003

Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Resonant clocking using distributed parasitic capacitance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.
J. VLSI Signal Process., 2002

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.
IEEE J. Solid State Circuits, 2002

2001
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A fast hybrid carry-lookahead/carry-select adder design.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Leading Zero Anticipation and Detection-A Comparison of Methods.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
Custom circuit design as a driver of microprocessor performance.
IBM J. Res. Dev., 2000

"Timing closure by design, " a high frequency microprocessor design methodology.
Proceedings of the 37th Conference on Design Automation, 2000

A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Beyond 1 GHz.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Designing for a gigahertz [guTS integer processor].
IEEE Micro, 1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.
IEEE J. Solid State Circuits, 1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Design methodology for a 1.0 GHz microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Circuit design techniques for a gigahertz integer microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Circuits and Microarchitecture for Gigahertz VLSI Designs.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1995
System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

The SNAP Project: Towards Sub-Nanosecond Arithmetic.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995


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