Eric M. Schwarz

According to our database1, Eric M. Schwarz authored at least 36 papers between 1988 and 2015.

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Bibliography

2015
The SIMD accelerator for business analytics on the IBM z13.
IBM J. Res. Dev., 2015

2011
The zEnterprise 196 System and Microprocessor.
IEEE Micro, 2011


2010
A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit.
J. Signal Process. Syst., 2010

A survey of hardware designs for decimal arithmetic.
IBM J. Res. Dev., 2010

2009
Decimal floating-point support on the IBM System z10 processor.
IBM J. Res. Dev., 2009

2007
IBM POWER6 microarchitecture.
IBM J. Res. Dev., 2007

IBM POWER6 accelerators: VMX and DFU.
IBM J. Res. Dev., 2007

Power6 Decimal Divide.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

P6 Binary Floating-Point Unit.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
FPU Implementations with Denormalized Numbers.
IEEE Trans. Computers, 2005

Decimal Multiplication with Efficient Partial Product Generation.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
The IBM eServer z990 floating-point unit.
IBM J. Res. Dev., 2004

2003
Hardware Implementations of Denormalized Numbers.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

Panel: Revisions to the IEEE 754 Standard for Floating-Point Arithmetic.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

High Performance Floating-Point Unit with 116 Bit Wide Divider.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002
The microarchitecture of the IBM eServer z900 processor.
IBM J. Res. Dev., 2002

2001
A Decimal Floating-Point Specification.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

1999
IBM's S/390 G5 microprocessor design.
IEEE Micro, 1999

The S/390 G5 floating-point unit.
IBM J. Res. Dev., 1999

The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1997
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders.
IEEE J. Solid State Circuits, 1997

CMOS floating-point unit for the S/390 Parallel Enterprise Server G4.
IBM J. Res. Dev., 1997

A Radix-8 CMOS S/390 Multiplier.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996
Hardware Starting Approximation Method and Its Application to the Square Root Operation.
IEEE Trans. Computers, 1996

1995
The SNAP Project: Towards Sub-Nanosecond Arithmetic.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1993
Parallel High-Radix Nonrestoring Division.
IEEE Trans. Computers, 1993

Hardware starting approximation for the square root operation.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1991
Cost-efficient high-radix division.
J. VLSI Signal Process., 1991

Hard-Wired Multipliers with Encoded Partial Products.
IEEE Trans. Computers, 1991

1990
ATPG Aspects of FSM Verification.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Results on the Interface between Formal Verification and ATPG.
Proceedings of the Computer-Aided Verification, 1990

1989
A General Proof for Overlapped Multiple-Bit Scanning Multiplications.
IEEE Trans. Computers, 1989

On optimal extraction of combinational logic and don't care sets from hardware description languages.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Parallel Encryted Array Multipliers.
IBM J. Res. Dev., 1988


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