Masami Urano

According to our database, Masami Urano authored at least 9 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.

Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2015

Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip.

Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata

IEICE Trans. Electron., 2015

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.

Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2013

A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI.

Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata

IEICE Electron. Express, 2013

2012

Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs.

Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.

Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata

Proceedings of the International SoC Design Conference, 2011

Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction.

Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Akihiko Miyazaki, Masami Urano, Tsugumichi Shibata

Proceedings of the Global Communications Conference, 2011

A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON.

Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011