According to our database1, Masami Urano authored at least 9 papers between 2011 and 2017.
Legend:Book In proceedings Article PhD thesis Other
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Electron., 2015
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI.
IEICE Electron. Express, 2013
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.
Proceedings of the International SoC Design Conference, 2011
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction.
Proceedings of the Global Communications Conference, 2011
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011