Naoki Miura

Orcid: 0000-0001-6676-9734

According to our database1, Naoki Miura authored at least 22 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Japanese-English Sentence Translation Exercises Dataset for Automatic Grading.
Proceedings of the 18th Conference of the European Chapter of the Association for Computational Linguistics, 2024

2021
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation.
IEEE J. Solid State Circuits, 2021

2020
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
IEICE Trans. Electron., 2020

2019
A 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2015
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip.
IEICE Trans. Electron., 2015

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2014
Effectiveness of SIEPON Package B Compliant ONU Sleep Technique and Impact on Latency and Transmission Efficiency from a Theoretical Point of View.
JOCN, 2014

2012
Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Second-language Instinct and Instruction Effects: Nature and Nurture in Second-language Acquisition.
J. Cogn. Neurosci., 2011

2009
Analyzing Control-Display Movement Compatibility: A Neuroimaging Study.
Proceedings of the Engineering Psychology and Cognitive Ergonomics, 2009

2008
An advantage of bipedal humanoid robot on the empathy generation: A neuroimaging study.
Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008

2006
Multiple brain networks for visual self-recognition with different sensitivity for motion and body part.
NeuroImage, 2006

2005
Cortical activation during reading of ancient versus modern Japanese texts: fMRI study.
NeuroImage, 2005

2004
The human parietal cortex is involved in spatial processing of tongue movement - an fMRI study.
NeuroImage, 2004

A state-space model of the hemodynamic approach: nonlinear filtering of BOLD signals.
NeuroImage, 2004

Aware-Mail: An Event-Driven Mail System for Wearable Computing Environments.
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004


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