Masoud Zamani

According to our database, Masoud Zamani authored at least 14 papers between 2008 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Quantifying Local Strain Field and Deformation in Active Contraction of Bladder Using a Pretrained Transformer Model: A Speckle-Free Approach.

Alireza Asadbeygi, Anne M. Robertson, Yasutaka Tobe, Masoud Zamani, Sean D. Stocker, Paul N. Watton, Naoki Yoshimura, Simon C. Watkins

CoRR, January, 2026

2013

ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures.

Masoud Zamani, Hanieh Mirzaei, Mehdi Baradaran Tahoori

ACM J. Emerg. Technol. Comput. Syst., 2013

2012

Ping-pong test: Compact test vector generation for reversible circuits.

Masoud Zamani, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Reliable logic mapping on Nano-PLA architectures.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Self-timed nano-PLA.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Fault Masking and Diagnosis in Reversible Circuits.

Masoud Zamani, Navid Farazmand, Mehdi Baradaran Tahoori

Proceedings of the 16th European Test Symposium, 2011

Online Missing/Repeated Gate Faults Detection in Reversible Circuits.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Templated-Based Asynchronous Design for Testable and Fail-Safe Operation.

Masoud Zamani, Hossein Pedram, Fabrizio Lombardi

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Variation-aware logic mapping for crossbar nano-architectures.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Online fault testing of reversible logic using dual rail coding.

Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A transient error tolerant self-timed asynchronous architecture.

Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 15th European Test Symposium, 2010

Online Multiple Fault Detection in Reversible Circuits.

Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2008

A novel test environment for template based QDI asynchronous circuits.

Ali-Asghar Salehpour, Masoud Zamani, Amir-Mohammad Rahmani, Siamak Mohammadi, Hossein Pedram, Mohammadreza Binesh Marvasti

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008