Mehdi Baradaran Tahoori

According to our database1, Mehdi Baradaran Tahoori authored at least 318 papers between 2002 and 2020.

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Bibliography

2020
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Printed Camouflaged Cell Against Reverse Engineering of Printed Electronics Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection.
ACM Trans. Design Autom. Electr. Syst., 2020

Reverse Engineering of Printed Electronics Circuits: From Imaging to Netlist Extraction.
IEEE Trans. Inf. Forensics Secur., 2020

CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Selective Flip-Flop Optimization for Reliable Digital Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Approximate Spintronic Memories.
ACM J. Emerg. Technol. Comput. Syst., 2020

Crossover-aware Placement and Routing for Inkjet Printed Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2020

Remote Electrical-level Security Threats to Multi-Tenant FPGAs.
IEEE Des. Test, 2020

Fabrication, Characterization and Simulation of Sputtered Pt/In-Ga-Zn-O Schottky Diodes for Low-Frequency Half-Wave Rectifier Circuits.
IEEE Access, 2020

Mitigating Read Failures in STT-MRAM.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Printed Machine Learning Classifiers.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Printed Microprocessors.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Defect Characterization of Spintronic-based Neuromorphic Circuits.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory.
Proceedings of the IEEE European Test Symposium, 2020

Testing Scouting Logic-Based Computation-in-Memory Architectures.
Proceedings of the IEEE European Test Symposium, 2020

Hardware-Intrinsic Security with Printed Electronics for Identification of IoE Devices.
Proceedings of the European Conference on Circuit Theory and Design, 2020

A Universal Spintronic Technology based on Multifunctional Standardized Stack.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance Sampling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Programmable Neuromorphic Circuit based on Printed Electrolyte-Gated Transistors.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud.
ACM Trans. Reconfigurable Technol. Syst., 2019

Dependability Analysis of Data Storage Systems in Presence of Soft Errors.
IEEE Trans. Reliab., 2019

Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.
ACM Trans. Design Autom. Electr. Syst., 2019

Leaky Noise: New Side-Channel Attack Vectors in Mixed-Signal IoT Devices.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems.
IEEE Trans. Computers, 2019

Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs.
IACR Cryptol. ePrint Arch., 2019

Voltage-based Covert Channels in Multi-Tenant FPGAs.
IACR Cryptol. ePrint Arch., 2019

Image PUF: A Physical Unclonable Function for Printed Electronics based on Optical Variation of Printed Inks.
IACR Cryptol. ePrint Arch., 2019

Testing of Neuromorphic Circuits: Structural vs Functional.
Proceedings of the IEEE International Test Conference, 2019

IEEE European Test Symposium (ETS).
Proceedings of the IEEE International Test Conference, 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Predictive Modeling and Design Automation of Inorganic Printed Electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Test Pattern Generation for Approximate Circuits Based on Boolean Satisfiability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reliable in-memory neuromorphic computing using spintronics.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Fine-Grained Energy-Constrained Microprocessor Pipeline Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.
ACM Trans. Design Autom. Electr. Syst., 2018

FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level.
IACR Cryptol. ePrint Arch., 2018

An Inside Job: Remote Power Analysis Attacks on FPGAs.
IACR Cryptol. ePrint Arch., 2018

Optimizing Datapaths for Near Threshold Computing.
Proceedings of the 15th International Conference on Synthesis, 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018

Reliable memory PUF design for low-power applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and evaluation of physical unclonable function for inorganic printed electronics.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A cross-layer adaptive approach for performance and power optimization in STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parametric failure modeling and yield analysis for STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-bit non-volatile spintronic flip-flop.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Spintronic normally-off heterogeneous system-on-chip design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Runtime adjustment of IoT system-on-chips for minimum energy operation.
Proceedings of the 55th Annual Design Automation Conference, 2018

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Balancing resiliency and energy efficiency of functional units in ultra-low power systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Bias Temperature Instability Mitigation via Adaptive Cache Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocess. Microsystems, 2017

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods.
Integr., 2017

Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Run-time hardware trojan detection using performance counters.
Proceedings of the IEEE International Test Conference, 2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Architecting SOT-RAM Based GPU Register File.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Post-fabrication calibration of Near-Threshold circuits for energy efficiency.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Design flows for resilient energy-efficient systems.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Leveraging recovery effect to reduce electromigration degradation in power/ground TSV.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Voltage drop-based fault attacks on FPGAs using valid bitstreams.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Energy Efficient Scientific Computing on FPGAs using OpenCL.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Exploiting STT-MRAM for approximate computing.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Aging-aware coding scheme for memory arrays.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Recovery-aware proactive TSV repair for electromigration in 3D ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Opportunistic write for fast and reliable STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Leveraging aging effect to improve SRAM-based true random number generators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Computing with nano-crossbar arrays: Logic synthesis and fault tolerance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing.
Proceedings of the 54th Annual Design Automation Conference, 2017

Post Silicon Debugging of Electrical Bugs Using Trace Buffers.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Workload-aware static aging monitoring of timing-critical flip-flops.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Self-Timed Read and Write Operations in STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2016

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016

On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Layout-Based Modeling and Mitigation of Multiple Event Transients.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Built-In Self-Heating Thermal Testing of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Online soft-error vulnerability estimation for memory arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test implications and challenges in near threshold computing special session.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Fault tolerant approximate computing using emerging non-volatile spintronic memories.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Hold-time violation analysis and fixing in near-threshold region.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Architecting STT Last-Level-Cache for performance and energy improvement.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Instruction cache aging mitigation through Instruction Set Encoding.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A cross-layer approach for resiliency and energy efficiency in near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Analysis of transient voltage fluctuations in FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

System-level reliability evaluation through cache-aware software-based fault injection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Thermal-aware TSV repair for electromigration in 3D ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Cross-Layer Approaches for an Aging-Aware Design Space Exploration for Microprocessors.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Variation-aware near threshold circuit synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fault Tolerant Non-Volatile spintronic flip-flop.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Cross-layer approaches for soft error modeling and mitigation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Fault injection acceleration by simultaneous injection of non-interacting faults.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Area-energy tradeoffs of logic wear-leveling for BTI-induced aging.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Test and Reliability Issues in 2.5D and 3D Integration.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design.
ACM Trans. Design Autom. Electr. Syst., 2015

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2015

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Application-aware cross-layer reliability analysis and optimization.
it Inf. Technol., 2015

Extending standard cell library for aging mitigation.
IET Comput. Digit. Tech., 2015

Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths.
J. Electron. Test., 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.
IEEE Des. Test, 2015

Resiliency challenges in sub-10nm technologies.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist.
Proceedings of the 2015 IEEE International Test Conference, 2015

Stepped parity: A low-cost multiple bit upset detection technique.
Proceedings of the 2015 IEEE International Test Conference, 2015

Analysis and optimization of flip-flops under process and runtime variations.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Cross-layer resilient system design flow.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Self-awareness and self-learning for resiliency in real-time systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Deadspace-aware Power/Ground TSV planning in 3D floorplanning.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Defect Clustering-Aware Spare-TSV Allocation for 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Aging guardband reduction through selective flip-flop optimization.
Proceedings of the 20th IEEE European Test Symposium, 2015

Re-using BIST for circuit aging monitoring.
Proceedings of the 20th IEEE European Test Symposium, 2015

Reliability-aware operation chaining in high level synthesis.
Proceedings of the 20th IEEE European Test Symposium, 2015

Protecting caches against multi-bit errors using embedded erasure coding.
Proceedings of the 20th IEEE European Test Symposium, 2015

High-resolution online power monitoring for modern microprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

On-line prediction of NBTI-induced aging rates.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Fault injection acceleration by architectural importance sampling.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Stress-aware P/G TSV planning in 3D-ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Introduction to Special Issue on Cross-layer Dependable Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2014

Aging-Aware Design of Microprocessor Instruction Pipelines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014

Introduction to the Special Issue on Reversible Computation.
ACM J. Emerg. Technol. Comput. Syst., 2014

Effect of the Active Layer on Carbon Nanotube-Based Cells for Yield Analysis.
ACM J. Emerg. Technol. Comput. Syst., 2014

Towards Cross-layer Reliability Analysis of Transient and Permanent Faults.
CoRR, 2014

On-chip voltage-droop prediction using support-vector machines.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Self-heating thermal-aware testing of FPGAs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Physical design of CNTFET-based circuits for yield improvement.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Read disturb fault detection in STT-MRAM.
Proceedings of the 2014 International Test Conference, 2014

Chip Health Monitoring Using Machine Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Avoiding unnecessary write operations in STT-MRAM for low power implementation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Aging effects in FPGAs: an experimental analysis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Towards dark silicon era in FPGAs using complementary hard logic design.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Quantitative evaluation of register vulnerabilities in RTL control paths.
Proceedings of the 19th IEEE European Test Symposium, 2014

P/G TSV planning for IR-drop reduction in 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Aging-aware standard cell library design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A power-efficient reconfigurable architecture using PCM configuration technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Reliability-aware Register Binding for Control-Flow Intensive Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Adaptive Mitigation of Parameter Variations.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

ArISE: Aging-aware instruction set encoding for lifetime improvement.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Architectural aspects in design and analysis of SOT-based memories.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach.
J. Low Power Electron., 2013

ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures.
ACM J. Emerg. Technol. Comput. Syst., 2013

Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit.
ACM J. Emerg. Technol. Comput. Syst., 2013

CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis.
J. Electron. Test., 2013

Chip-level modeling and analysis of electrical masking of soft errors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Representative critical-path selection for aging-induced delay monitoring.
Proceedings of the 2013 IEEE International Test Conference, 2013

Aging-aware timing analysis considering combined effects of NBTI and PBTI.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Aging-aware logic synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Altering LUT configuration for wear-out mitigation of FPGA-mapped designs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview).
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing.
Proceedings of the 18th IEEE European Test Symposium, 2013

Cross-layer resilient system design.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

MTTF-balanced pipeline design.
Proceedings of the Design, Automation and Test in Europe, 2013

Instruction-set extension under process variation and aging effects.
Proceedings of the Design, Automation and Test in Europe, 2013

Incorporating the impacts of workload-dependent runtime variations into timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A layout-based approach for multiple event transient analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

CLASS: Combined logic and architectural soft error sensitivity analysis.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Efficient algorithms to accurately compute derating factors of digital circuits.
Microelectron. Reliab., 2012

Ping-pong test: Compact test vector generation for reversible circuits.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

An efficient probability framework for error propagation and correlation estimation.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Reliable logic mapping on Nano-PLA architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

High-level aging estimation for FPGA-mapped designs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Online detection and recovery of transient errors in front-end structures of microprocessors.
Proceedings of the 17th IEEE European Test Symposium, 2012

Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation.
Proceedings of the 17th IEEE European Test Symposium, 2012

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

NBTI mitigation by optimized NOP assignment and insertion.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
High Resolution Application Specific Fault Diagnosis of FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Numerical Defect Correction as an Algorithm-Based Fault Tolerance Technique for Iterative Solvers.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

Self-timed nano-PLA.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Modeling and estimation of power supply noise using linear programming.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A linear programming approach for minimum NBTI vector selection.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Investigation of NBTI and PBTI induced aging in different LUT implementations.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault Masking and Diagnosis in Reversible Circuits.
Proceedings of the 16th European Test Symposium, 2011

Online Missing/Repeated Gate Faults Detection in Reversible Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).
Proceedings of the Design, Automation and Test in Europe, 2011


Variation-aware logic mapping for crossbar nano-architectures.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Variation and defect tolerance for diode-based nano crossbars.
Nano Commun. Networks, 2010

Using Boolean satisfiability for computing soft error rates in early design stages.
Microelectron. Reliab., 2010

Soft error modeling and remediation techniques in ASIC designs.
Microelectron. J., 2010

On-the-fly variation tolerant mapping in crossbar nano-architectures.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Soft error reliability aware placement and routing for FPGAs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Online fault testing of reversible logic using dual rail coding.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A transient error tolerant self-timed asynchronous architecture.
Proceedings of the 15th European Test Symposium, 2010

Multiple fault diagnosis in crossbar nano-architectures.
Proceedings of the 15th European Test Symposium, 2010

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Online Multiple Fault Detection in Reversible Circuits.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Panel: Reliability of data centers: Hardware vs. software.
Proceedings of the Design, Automation and Test in Europe, 2010

Variation tolerant logic mapping for crossbar array nano architectures.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Obtaining FPGA soft error rate in high performance information systems.
Microelectron. Reliab., 2009

Low-overhead defect tolerance in crossbar nanoarchitectures.
ACM J. Emerg. Technol. Comput. Syst., 2009

Online detection of multiple faults in crossbar nano-architectures using dual rail implementations.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Online multiple error detection in crossbar nano-architectures.
Proceedings of the 27th International Conference on Computer Design, 2009

BISM: built-in self map for hybrid crossbar nano-architectures.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Soft error rate computation in early design stages using boolean satisfiability.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Transient Error Detection and Recovery in Processor Pipelines.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems.
Proceedings of the 2008 IEEE International Test Conference, 2008

Obtaining Microprocessor Vulnerability Factor Using Formal Methods.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Application-Dependent Delay Testing of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Case Study: Soft Error Rate Analysis in Storage Systems.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Estimating Error Propagation Probabilities with Bounded Variances.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Application-Dependent Testing of FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Reducing Data Cache Susceptibility to Soft Errors.
IEEE Trans. Dependable Secur. Comput., 2006

Application-independent defect tolerance of reconfigurable nanoarchitectures.
ACM J. Emerg. Technol. Comput. Syst., 2006

Test Compression for FPGAs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Soft error hardening for logic-level designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Application-independent defect-tolerant crossbar nano-architectures.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Soft error derating computation in sequential circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Vulnerability analysis of L2 cache elements to single event upsets.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Application-independent testing of FPGA interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A probabilistic analysis of fault tolerance for switch block array in FPGAs.
Int. J. Embed. Syst., 2005

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Des. Test Comput., 2005

Soft Error Mitigation for SRAM-Based FPGAs.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Balancing Performance and Reliability in the Memory Hierarchy.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

An analytical approach for soft error rate estimation in digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Soft error rate estimation and mitigation for SRAM-based FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defects, Yield, and Design in Sublithographic Nano-electronics.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A Low Power Soft Error Suppression Technique for Dynamic Logic.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Soft Error Modeling and Protection for Sequential Elements.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

An Accurate SER Estimation Method Based on Propagation Probability.
Proceedings of the 2005 Design, 2005

2004
Techniques and algorithms for fault grading of FPGA interconnect test configurations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Application-Specific Bridging Fault Testing of FPGAs.
J. Electron. Test., 2004

A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Defects and Faults in Quantum Cellular Automata at Nano Scale.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Interconnect Delay Testing of Designs on Programmable Logic Devices.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Application-Dependent Diagnosis of FPGAs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Routability and Fault Tolerance of FPGA Interconnect Architectures.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Quantum Cellular Automata: New Defects and Faults for New Devices.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Design and characterization of an and-or-inverter (AOI) gate for QCA implementation.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Defect and Fault Tolerance of Reconfigurable Molecular Computing.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Defect Characterization for Scaling of QCA Devices.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Testing of Quantum Dot Cellular Automata Based Designs.
Proceedings of the 2004 Design, 2004

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.
Proceedings of the 2004 Design, 2004

Fault Tolerance of Programmable Switch Blocks.
Proceedings of the 2004 Design, 2004

2003
Automatic Configuration Generation for FPGA Interconnect Testing.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Application-dependent testing of FPGAs for bridging faults.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A high resolution diagnosis technique for open and short defects in FPGA interconnects.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Application-Dependent Testing of FPGA Interconnects.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Using satisfiability in application-dependent testing of FPGA interconnects.
Proceedings of the 40th Design Automation Conference, 2003

2002
Fault Grading FPGA Interconnect Test Configurations.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Testing for resistive open defects in FPGAs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Diagnosis of open defects in FPGA interconnect.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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