Mateus Fonseca

According to our database, Mateus Fonseca authored at least 16 papers between 2005 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Modeling and Evaluating Personas with Software Explainability Requirements.

Henrique Ramos, Mateus Fonseca, Lesandro Ponciano

CoRR, 2021

2019

IIR Filter Architectures with Truncation Error Feedback for ECG Signal Processing.

Gustavo Ott, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Mateus Beck Fonseca

Circuits Syst. Signal Process., 2019

Hyperparameter Tuning and its Effects on Cardiac Arrhythmia Prediction.

Renan Soares de Andrades, Mateus Grellert, Mateus Beck Fonseca

Proceedings of the 8th Brazilian Conference on Intelligent Systems, 2019

2017

A power-efficient 4-2 Adder Compressor topology.

Raphael Dornelles, Guilherme Paim, Bianca Silveira, Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies.

Renato H. Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Jean P. Oses

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Low power sum of absolute differences architecture using novel hybrid adder.

Rafael Ferreira, Bianca Silveira, Mateus Beck Fonseca, Cláudio Machado Diniz, Eduardo A. C. da Costa

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.

Gustavo M. Santana, Guilherme Paim, Leandro M. G. Rocha, Renato Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Sergio Bampi

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

Exploiting adder compressors for power-efficient 2-D approximate DCT realization.

Tiago Schiavon, Guilherme Paim, Mateus Fonseca, Eduardo A. C. da Costa, Sérgio J. M. de Almeida

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Exploiting architectural solutions for IIR filter architecture with truncation error feedback.

Gustavo Ott, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Mateus Fonseca

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time.

Renato Neuenfeld, Mateus Fonseca, Eduardo A. C. da Costa

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.

Cláudio Machado Diniz, Mateus Beck Fonseca, Eduardo A. C. da Costa, Sergio Bampi

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder.

Bianca Silveira, Cláudio Machado Diniz, Mateus Fonseca, Eduardo A. C. da Costa

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Power efficient 2-D rounded cosine transform with adder compressors for image compression.

Guilherme Paim, Mateus Fonseca, Eduardo A. C. da Costa, Sérgio J. M. de Almeida

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization.

Anderson Martins, Mateus Fonseca, Eduardo A. C. da Costa

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Floating-point adaptive filter architectures for the cancelling of harmonics power line interference.

Vagner Guidotti, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Mateus Fonseca

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2005

Design of a radix-2^m hybrid array multiplier using carry save adder format.

Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005