Leandro M. G. Rocha

According to our database1, Leandro M. G. Rocha authored at least 22 papers between 2017 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2020

Binary CorNET: Accelerator for HR Estimation From Wrist-PPG.
IEEE Trans. Biomed. Circuits Syst., 2020

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding.
J. Real Time Image Process., 2020

Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling.
Circuits Syst. Signal Process., 2020

Improving the Partial Product Tree Compression on Signed Radix-2<sup>m</sup> Parallel Multipliers.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

The Radix-2<sup>m</sup> Squared Multiplier.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Real-time HR Estimation from wrist PPG using Binary LSTMs.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017
A power-predictive environment for fast and power-aware ASIC-based FIR filter design.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017


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