Cláudio Machado Diniz
Orcid: 0000-0002-5019-3715
According to our database1,
Cláudio Machado Diniz
authored at least 45 papers
between 2007 and 2023.
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Bibliography
2023
A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard.
Proceedings of the 28th European Signal Processing Conference, 2020
2019
Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Exploring the use of parallel prefix adder topologies into approximate adder circuits.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A deblocking filter hardware architecture for the high efficiency video coding standard.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms.
Int. J. Parallel Program., 2014
Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC.
Proceedings of the IEEE International Conference on Image Processing, 2013
2012
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
VLSI Design, 2012
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfigurable Comput., 2012
Proceedings of the 19th IEEE International Conference on Image Processing, 2012
2011
Applying CUDA Architecture to Accelerate Full Search Block Matching Algorithm for High Performance Motion Estimation in Video Encoding.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
2010
Timing and interface communication analysis of H.264/AVC encoder using SystemC model.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
2007
A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007