Guilherme Paim
Orcid: 0000-0001-7809-9563
According to our database1,
Guilherme Paim
authored at least 75 papers
between 2015 and 2023.
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Bibliography
2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Energy-Efficient VLSI Squarer Unit with Optimized Radix-2<sup>m</sup> Multiplication Logic.
Circuits Syst. Signal Process., February, 2023
ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Trans. Very Large Scale Integr. Syst., 2023
Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2022
Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop.
IEEE Trans. Circuits Syst. Video Technol., 2022
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
C2PAx: Complexity-Aware Constant Parameter Approximation for Energy-Efficient Tree-Based Machine Learning Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers.
IEEE Trans. Computers, 2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022
Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Energy-Efficient Haar Wavelet Transform Architecture for Respiratory Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Biomed. Circuits Syst., 2021
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors.
IET Comput. Digit. Tech., 2021
Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals.
Circuits Syst. Signal Process., 2021
Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
2020
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2020
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding.
J. Real Time Image Process., 2020
Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling.
Circuits Syst. Signal Process., 2020
Improving the Partial Product Tree Compression on Signed Radix-2<sup>m</sup> Parallel Multipliers.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019
Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 2018 New Generation of CAS, 2018
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A power-predictive environment for fast and power-aware ASIC-based FIR filter design.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015
Power efficient 2-D rounded cosine transform with adder compressors for image compression.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015