Guilherme Paim

According to our database1, Guilherme Paim authored at least 46 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
An Energy-Efficient Haar Wavelet Transform Architecture for Respiratory Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2020

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding.
J. Real Time Image Process., 2020

Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling.
Circuits Syst. Signal Process., 2020

Improving the Partial Product Tree Compression on Signed Radix-2<sup>m</sup> Parallel Multipliers.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

The Radix-2<sup>m</sup> Squared Multiplier.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019

Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series.
Proceedings of the 2018 New Generation of CAS, 2018

Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A power-predictive environment for fast and power-aware ASIC-based FIR filter design.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A power-efficient 4-2 Adder Compressor topology.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Improved goldschmidt algorithm for fast and energy-efficient fixed-point divider.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Exploiting absolute arithmetic for power-efficient sum of absolute differences.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Exploiting adder compressors for power-efficient 2-D approximate DCT realization.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Power-efficient sum of absolute differences architecture using adder compressors.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A multi-standard interpolation hardware solution for H.264 and HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

Power efficient 2-D rounded cosine transform with adder compressors for image compression.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


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