Barry John Muldrey
Orcid: 0000-0003-2052-6096
According to our database1,
Barry John Muldrey
authored at least 29 papers
between 2012 and 2023.
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Bibliography
2023
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems.
J. Electron. Test., June, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
2022
Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design.
IEEE Access, 2022
Toward the creation of a novel electric bike rental program to ease university congestion.
Proceedings of the ACM SE '22: 2022 ACM Southeast Conference, Virtual Event, April 18, 2022
2021
J. Electron. Test., 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
Algorithms for Post-silicon Validation and Debug of Radio-frequency, analog, and mixed-signal Circuits and Systems.
PhD thesis, 2019
Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
2017
Self-Learning RF Receiver Systems: Process Aware Real-Time Adaptation to Channel Conditions for Low Power Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization.
Proceedings of the IEEE International Test Conference, 2017
BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems.
Proceedings of the 2016 IEEE International Test Conference, 2016
Trojan detection in digital systems using current sensing of pulse propagation in logic gates.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware.
J. Electron. Test., 2015
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
2012
Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012