Meishoku Masahara

Orcid: 0000-0003-2160-5730

According to our database1, Meishoku Masahara authored at least 15 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Power-efficient gray-scale control of silicon thermo-optic phase shifters by pulse width modulation using monolithically integrated MOSFET.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

PBTI for N-type tunnel FinFETs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Independent-Double-Gate FinFET SRAM Technology.
IEICE Trans. Electron., 2013

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations.
Proceedings of the European Solid-State Device Research Conference, 2013

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
High-Frequency Precise Characterization of Intrinsic FinFET Channel.
IEICE Trans. Electron., 2012

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology.
IEICE Trans. Electron., 2012

Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2010
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction.
IEICE Trans. Electron., 2008

2007
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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