Hanpei Koike

According to our database1, Hanpei Koike authored at least 41 papers between 1986 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.
IEICE Transactions, 2018

2016
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology.
IEICE Transactions, 2016

Implementation of pseudo linear feedback shift register physical unclonable function on silicon.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs.
IEICE Electronic Express, 2015

Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2013
Fully-functional FPGA prototype with fine-grain programmable body biasing.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
High-Frequency Precise Characterization of Intrinsic FinFET Channel.
IEICE Transactions, 2012

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology.
IEICE Transactions, 2012

2010
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Development of a CAD tool for 3D-FPGAs.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
High-speed low-power FinFET based domino logic.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
TRETS, 2008

FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction.
IEICE Transactions, 2008

2007
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA.
IEICE Transactions, 2007

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Optimal set of body bias voltages for an FPGA with field-programmable Vth components.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Evaluation of granularity on threshold voltage control in flex power FPGA.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

FPGAs with multidimensional mesh topology.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Evaluation of granularity on threshold voltage control in flex power FPGA.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity.
IEICE Transactions, 2004

Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

1998
Fast Speculative Search Engine on the Highly Parallel Computer EM-X.
Proceedings of the SIGIR '98: Proceedings of the 21st Annual International ACM SIGIR Conference on Research and Development in Information Retrieval, 1998

1997
Parallel Execution of Radix Sort Program Using Fine-Grain Communication.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1994
Architecture of parallel management kernel for PIE64.
Future Generation Comp. Syst., 1994

A Performance Debugger for a Parallel Logic Programming Language Fleng.
Proceedings of the Theory and Practice of Parallel Programming, 1994

A Fleng Compiler for PIE64.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1993
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64.
New Generation Comput., 1993

Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU.
Proceedings of the PARLE '93, 1993

Multiple Threads in Cyclic Register Windows.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

The Instruction Set Architecture of the Inference Processor UNIRED II.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

1992
HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs.
Proceedings of the Programming Environments for Parallel Computing, 1992

Architecture of Parallel Management Kernel for PIE64.
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64.
FGCS, 1992

1991
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages.
Proceedings of the Logic Programming, Proceedings of the 1991 International Symposium, San Diego, California, USA, Oct. 28, 1991

1989
Distributed Garbage Collection for the Parallel Inference Engine PIE64.
Proceedings of the Logic Programming, 1989

Distributed Garbage Collection for the Parallel Inference Machine PIE64.
IFIP Congress, 1989

1988
Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64.
FGCS, 1988

1986
Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting.
Proceedings of the Logic Programming '86, 1986


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