Shin-ichi O'Uchi

According to our database1, Shin-ichi O'Uchi authored at least 21 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Perturbative GAN: GAN with Perturbation Layers.
CoRR, 2019

Optimizing Weight Value Quantization for CNN Inference.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2015
PBTI for N-type tunnel FinFETs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Independent-Double-Gate FinFET SRAM Technology.
IEICE Trans. Electron., 2013

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations.
Proceedings of the European Solid-State Device Research Conference, 2013

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
High-Frequency Precise Characterization of Intrinsic FinFET Channel.
IEICE Trans. Electron., 2012

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology.
IEICE Trans. Electron., 2012

2010
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction.
IEICE Trans. Electron., 2008

2007
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
CMOS Integrated DNA Chip for Quantitative DNA Analysis.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2002
An 8-qubit quantum-circuit processor.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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