Mengjia Yan

Orcid: 0000-0002-6206-9674

Affiliations:
  • Massachusetts Institute of Technology, Cambridge, MA, USA
  • University of Illinois at Urbana-Champaign, IL, USA (PhD)
  • Zhejiang University, College of Computer Science and Technology, Hangzhou, China (former)


According to our database1, Mengjia Yan authored at least 34 papers between 2013 and 2025.

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Timeline

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Bibliography

2025
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches.
IEEE Des. Test, February, 2025

Oreo: Protecting ASLR Against Microarchitectural Attacks.
Proceedings of the 32nd Annual Network and Distributed System Security Symposium, 2025

RTL Verification for Secure Speculation Using Contract Shadow Logic.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
Formal Verification for Secure Processors: A Guide for Computer Architects.
Computer, October, 2024

Oreo: Protecting ASLR Against Microarchitectural Attacks (Extended Version).
CoRR, 2024

Ditto: Elastic Confidential VMs with Secure and Dynamic CPU Scaling.
CoRR, 2024

Bridge the Future: High-Performance Networks in Confidential VMs without Trusted I/O devices.
CoRR, 2024

DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

SoK: Understanding Design Choices and Pitfalls of Trusted Execution Environments.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2023
PACMAN: Attacking ARM Pointer Authentication With Speculative Execution.
IEEE Micro, 2023

There's Always a Bigger Fish: A Clarifying Analysis of a Machine-Learning-Assisted Side-Channel Attack.
IEEE Micro, 2023

Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era.
CoRR, 2023

SecureLoop: Design Space Exploration of Secure DNN Accelerators.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Pensieve: Microarchitectural Modeling for Security Evaluation.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

EntryBleed: A Universal KASLR Bypass against KPTI on Linux.
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023

2022
Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects.
Proceedings of the 31st USENIX Security Symposium, 2022

DAGguise: mitigating memory timing side channels.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Speculative taint tracking (STT): a comprehensive protection for speculatively accessed data.
Commun. ACM, 2021

SpecTaint: Speculative Taint Analysis for Discovering Spectre Gadgets.
Proceedings of the 28th Annual Network and Distributed System Security Symposium, 2021

2020
MicroScope: Enabling Microarchitectural Replay Attacks.
IEEE Micro, 2020

Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures.
Proceedings of the 29th USENIX Security Symposium, 2020

Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Cache-based side channels: Modern attacks and defenses
PhD thesis, 2019

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World.
Proceedings of the 2019 IEEE Symposium on Security and Privacy, 2019

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum).
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Research problems and opportunities in NoC-based side channel attacks and defenses: lessons learned from cache-based side channels.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

SecDir: a secure directory to defeat directory side-channel attacks.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Record-Replay Architecture as a General Security Framework.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2013
Agent-Based Traffic Merging in Network-on-Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013


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