# Sharad Malik

According to our database

Collaborative distances:

^{1}, Sharad Malik authored at least 248 papers between 1988 and 2018.Collaborative distances:

## Awards

## ACM Fellow

ACM Fellow 2014, "For contributions to efficient and capable SAT solvers, and accurate embedded software models.".

## IEEE Fellow

IEEE Fellow 2002, "For contributions to electronic design automation techniques in logic and embedded software synthesis.".

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2018

Propositional SAT Solving.

Proceedings of the Handbook of Model Checking., 2018

Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs.

ACM Trans. Design Autom. Electr. Syst., 2018

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification.

CoRR, 2018

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware.

Proceedings of the 55th Annual Design Automation Conference, 2018

Lazy Self-composition for Security Verification.

Proceedings of the Computer Aided Verification - 30th International Conference, 2018

MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications.

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees.

JETC, 2017

IC3 - Flipping the E in ICE.

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

Trace-based Analysis of Memory Corruption Malware Attacks.

Proceedings of the Hardware and Software: Verification and Testing, 2017

Solving linear arithmetic with SAT-based model checking.

Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Malware detection using machine learning based analysis of virtual memory access patterns.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Evaluating matrix representations for error-tolerant computing.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Model checking unbounded concurrent lists.

STTT, 2016

On computing minimal independent support and its applications to sampling and counting.

Constraints, 2016

Verifying information flow properties of firmware using symbolic execution.

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Specification and modeling for systems-on-chip security verification.

Proceedings of the 53rd Annual Design Automation Conference, 2016

Constrained Sampling and Counting: Universal Hashing Meets SAT Solving.

Proceedings of the Beyond NP, 2016

2015

Boolean Satisfiability Solvers and Their Applications in Model Checking.

Proceedings of the IEEE, 2015

Constrained Sampling and Counting: Universal Hashing Meets SAT Solving.

CoRR, 2015

Error-Tolerant Processors: Formal Specification and Verification.

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Evaluating the security of logic encryption algorithms.

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Detecting Hardware Trojans: A Tale of Two Techniques.

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Optimizing dynamic trace signal selection using machine learning and linear programming.

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Hardware Trojan detection for gate-level ICs using signal correlation based clustering.

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Completeness bounds and sequentialization for model checking of interacting firmware and hardware.

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Fast Interpolating BMC.

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution.

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Boolean Satisfiability: Solvers and Extensions.

Proceedings of the Software Systems Safety, 2014

Reverse Engineering Digital Circuits Using Structural and Functional Analyses.

IEEE Trans. Emerging Topics Comput., 2014

Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom.

CoRR, 2014

All-SAT Using Minimal Blocking Clauses.

Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

An assertion language for debugging SDN applications.

Proceedings of the third workshop on Hot topics in software defined networking, 2014

Effective abstraction for response proof of communication fabrics.

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

In-Band Update for Network Routing Policy Migration.

Proceedings of the 22nd IEEE International Conference on Network Protocols, 2014

Silicon fault diagnosis using sequence interpolation with backbones.

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reduction of Resolution Refutations and Interpolants via Subsumption.

Proceedings of the Hardware and Software: Verification and Testing, 2014

Template-based circuit understanding.

Proceedings of the Formal Methods in Computer-Aided Design, 2014

An Adaptable Rule Placement for Software-Defined Networks.

Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Automated firmware testing using firmware-hardware interaction patterns.

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom.

Proceedings of the Automated Technology for Verification and Analysis, 2014

2013

Model Checking Unbounded Concurrent Lists.

Proceedings of the Model Checking Software - 20th International Symposium, 2013

Modeling Firmware as Service Functions and Its Application to Test Generation.

Proceedings of the Hardware and Software: Verification and Testing, 2013

WordRev: Finding word-level structures in a sea of bit-level gates.

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Abstractions for model checking SDN controllers.

Proceedings of the Formal Methods in Computer-Aided Design, 2013

Extracting useful computation from error-prone processors for streaming applications.

Proceedings of the Design, Automation and Test in Europe, 2013

Reverse engineering digital circuits using functional analysis.

Proceedings of the Design, Automation and Test in Europe, 2013

SAT Based Verification of Network Data Planes.

Proceedings of the Automated Technology for Verification and Analysis, 2013

2012

Boolean Satisfiability Solvers: Techniques and Extensions.

Proceedings of the Software Safety and Security - Tools for Analysis and Verification, 2012

Wolverine: Battling Bugs with Interpolants - (Competition Contribution).

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Parameterized Model Checking of Fine Grained Concurrency.

Proceedings of the Model Checking Software - 19th International Workshop, 2012

Verification and synthesis of firewalls using SAT and QBF.

Proceedings of the 20th IEEE International Conference on Network Protocols, 2012

Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation.

Proceedings of the Hardware and Software: Verification and Testing, 2012

Efficient predictive analysis for detecting nondeterminism in multi-threaded programs.

Proceedings of the Formal Methods in Computer-Aided Design, 2012

Specification and synthesis of hardware checkpointing and rollback mechanisms.

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

passert: A Tool for Debugging Parallel Programs.

Proceedings of the Computer Aided Verification - 24th International Conference, 2012

Verification of Computer Switching Networks: An Overview.

Proceedings of the Automated Technology for Verification and Analysis, 2012

Parallel Assertions for Architectures with Weak Memory Models.

Proceedings of the Automated Technology for Verification and Analysis, 2012

EPROF: An energy/performance/reliability optimization framework for streaming applications.

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Specification and encoding of transaction interaction properties.

Formal Methods in System Design, 2011

Towards Eliminating Configuration Errors in Cyber Infrastructure.

Proceedings of the 4th Symposium on Configuration Analytics and Automation, SafeConfig 2011, Arlington, VA, USA, October 31, 2011

Runtime Verification: A Computer Architecture Perspective.

Proceedings of the Runtime Verification - Second International Conference, 2011

Predictive analysis for detecting serializability violations through Trace Segmentation.

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Parallel assertions for debugging parallel programs.

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search.

Proceedings of the Hardware and Software: Verification and Testing, 2011

SAT-based techniques for determining backbones for post-silicon fault localisation.

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Post-silicon fault localisation using maximum satisfiability and backbones.

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Runtime checking of serializability in software transactional memory.

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Utility of transaction-level hardware models in refinement checking.

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009

Conflict-Driven Clause Learning SAT Solvers.

Proceedings of the Handbook of Satisfiability, 2009

Preface.

Formal Methods in System Design, 2009

Boolean satisfiability from theoretical hardness to practical success.

Commun. ACM, 2009

Supporting RTL flow compatibility in a microarchitecture-level design framework.

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Declarative Infrastructure Configuration Synthesis and Debugging.

J. Network Syst. Manage., 2008

Challenges and Solutions for Late- and Post-Silicon Design.

IEEE Design & Test of Computers, 2008

Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Hardware Verification: Techniques, Methodology and Solutions.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2008

Runtime Validation of Transactional Memory Systems.

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Runtime validation of memory ordering using constraint graph checking.

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.

ACM Trans. Design Autom. Electr. Syst., 2007

Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions.

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Verification Driven Formal Architecture and Microarchitecture Modeling.

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Automating Hazard Checking in Transaction-Level Microarchitecture Models.

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors.

The Compiler Design Handbook, 2nd ed., 2007

Architecture Description Languages for Retargetable Compilation.

The Compiler Design Handbook, 2nd ed., 2007

2006

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.

IEEE Trans. VLSI Syst., 2006

The Liberty Simulation Environment: A deliberate approach to high-level system modeling.

ACM Trans. Comput. Syst., 2006

Lemma Learning in SMT on Linear Constraints.

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

Solving Quantified Boolean Formulas with Circuit Observability Don't Cares.

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

On Solving the Partial MAX-SAT Problem.

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

Dependable Multithreaded Processing Using Runtime Validation.

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis.

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2005

Achieving Structural and Composable Modeling of Complex Systems.

International Journal of Parallel Programming, 2005

A Study of Architecture Description Languages from a Model-based Perspective.

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation.

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Complementary use of runtime validation and model checking.

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A Case for Runtime Validation of Hardware.

Proceedings of the Hardware and Software Verification and Testing, 2005

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks.

Proceedings of the 2005 Design, 2005

Considering Circuit Observability Don't Cares in CNF Satisfiability.

Proceedings of the 2005 Design, 2005

Efficient behavior-driven runtime dynamic voltage scaling policies.

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Symmetry Reduction in SAT-Based Model Checking.

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

The design of dynamically reconfigurable datapath coprocessors.

ACM Trans. Embedded Comput. Syst., 2004

Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling.

TACO, 2004

Guest Editors' Introduction: Exploring Synergies for Design Verification.

IEEE Design & Test of Computers, 2004

Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems.

Proceedings of the Theory and Applications of Satisfiability Testing, 2004

Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems.

Proceedings of the SAT 2004, 2004

A Comparative Study of 2QBF Algorithms.

Proceedings of the SAT 2004, 2004

Zchaff2004: An Efficient SAT Solver.

Proceedings of the Theory and Applications of Satisfiability Testing, 2004

A formal concurrency model based architecture description language for synthesis of software development tools.

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Achieving Structural and Composable Modeling of Complex Systems.

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing.

Proceedings of the 2004 Design, 2004

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Facilitating reuse in hardware models with enhanced type inference.

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.

IEEE Micro, 2003

Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms.

Proceedings of the Theory and Applications of Satisfiability Testing, 2003

Compile-time dynamic voltage scaling settings: opportunities and limits.

Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, 2003

Power-driven Design of Router Microarchitectures in On-chip Networks.

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications.

Proceedings of the 2003 Design, 2003

Modeling and Integration of Peripheral Devices in Embedded Systems.

Proceedings of the 2003 Design, 2003

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.

Proceedings of the 2003 Design, 2003

Automated synthesis of efficient binary decoders for retargetable software toolkits.

Proceedings of the 40th Design Automation Conference, 2003

Synthesizing operating system based device drivers in embedded systems.

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002

Limits of Using Signatures for Permutation Independent Boolean Comparison.

Formal Methods in System Design, 2002

Developing Architectural Platforms: A Disciplined Approach.

IEEE Design & Test of Computers, 2002

Orion: a power-performance simulator for interconnection networks.

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

From ASIC to ASIP: The Next Design Discontinuity.

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A hierarchical modeling framework for on-chip communication architectures.

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Conflict driven learning in a quantified Boolean Satisfiability solver.

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.

Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

Design Tools for Application Specific Embedded Processors.

Proceedings of the Embedded Software, Second International Conference, 2002

Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?

Proceedings of the 39th Design Automation Conference, 2002

Exploiting operation level parallelism through dynamically reconfigurable datapaths.

Proceedings of the 39th Design Automation Conference, 2002

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.

Proceedings of the 39th Design Automation Conference, 2002

Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation.

Proceedings of the Principles and Practice of Constraint Programming, 2002

The Quest for Efficient Boolean Satisfiability Solvers.

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

The Quest for Efficient Boolean Satisfiability Solvers.

Proceedings of the Automated Deduction, 2002

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors.

The Compiler Design Handbook, 2002

Architecture Description Languages for Retargetable Compilation.

The Compiler Design Handbook, 2002

2001

Using complete-1-distinguishability for FSM equivalence checking.

ACM Trans. Design Autom. Electr. Syst., 2001

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Application of BDDs in Boolean matching techniques for formal logic combinational verification.

STTT, 2001

Accelerating boolean satisfiability through application specific processing.

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Retargetable static timing analysis for embedded software.

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Efficient Conflict Driven Learning in Boolean Satisfiability Solver.

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Embedded Software Implementation Tools for Fully Programmable Application Specific Systems.

Proceedings of the Embedded Software, First International Workshop, 2001

Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks.

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design.

Proceedings of the 38th Design Automation Conference, 2001

Chaff: Engineering an Efficient SAT Solver.

Proceedings of the 38th Design Automation Conference, 2001

Optimal Live Range Merge for Address Register Allocation in Embedded Programs.

Proceedings of the Compiler Construction, 10th International Conference, 2001

2000

Exact memory size estimation for array computations.

IEEE Trans. VLSI Syst., 2000

Simultaneous reference allocation in code generation for dual data memory bank ASIPs.

ACM Trans. Design Autom. Electr. Syst., 2000

Processor Evaluation in an Embedded Systems Design Environment.

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Automated cache optimizations using CME driven diagnosis.

Proceedings of the 14th international conference on Supercomputing, 2000

Incremental CAD.

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Embedded systems education (panel abstract).

Proceedings of the 37th Conference on Design Automation, 2000

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.

Proceedings of the 2000 International Conference on Compilers, 2000

1999

Cache miss equations: a compiler framework for analyzing and tuning memory behavior.

ACM Trans. Program. Lang. Syst., 1999

Performance estimation of embedded software with instruction cache modeling.

ACM Trans. Design Autom. Electr. Syst., 1999

Using configurable computing to accelerate Boolean satisfiability.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Establishing latch correspondence for sequential circuits using distinguishing signatures.

Integration, 1999

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis.

Design Autom. for Emb. Sys., 1999

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library.

Design Autom. for Emb. Sys., 1999

CAD Techniques for Embedded System Design.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Exact Memory Size Estimation for Array Computations without Loop Unrolling.

Proceedings of the 36th Conference on Design Automation, 1999

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Exploiting Retiming in a Guided Simulation Based Validation Methodology.

Proceedings of the Correct Hardware Design and Verification Methods, 1999

Performance analysis of real-time embedded software.

Springer, ISBN: 978-0-7923-8382-6, 1999

1998

Code generation for fixed-point DSPs.

ACM Trans. Design Autom. Electr. Syst., 1998

Guarded evaluation: pushing power management to logic synthesis/design.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Solving Boolean Satisfiability with Dynamic Hardware Configurations.

Proceedings of the Field-Programmable Logic and Applications, 1998

Accelerating Boolean Satisfiability with Configurable Hardware.

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability.

Proceedings of the 35th Conference on Design Automation, 1998

Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity.

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997

Power analysis and minimization techniques for embedded DSP software.

IEEE Trans. VLSI Syst., 1997

Performance analysis of embedded software using implicit path enumeration.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Delay abstraction in combinational logic circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Dynamic Power Management for Microprocessors: A Case Study.

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Cache Miss Equations: An Analytical Representation of Cache Misses.

Proceedings of the 11th international conference on Supercomputing, 1997

Optimization of embedded DSP programs using post-pass data-flow analysis.

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software.

Proceedings of the Euro-Par '97 Parallel Processing, 1997

Static Timing Analysis of Embedded Software.

Proceedings of the 34st Conference on Design Automation, 1997

Toward Formalizing a Validation Methodology Using Simulation Coverage.

Proceedings of the 34st Conference on Design Automation, 1997

1996

Instruction level power analysis and optimization of software.

VLSI Signal Processing, 1996

Technology mapping for low power in logic synthesis.

Integration, 1996

Instruction Level Power Analysis and Optimization of Software.

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Register Transfer Level Synthesis: From Theory to Practice.

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Cache modeling for real-time software: beyond direct mapped instruction caches.

Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

Instruction Set Design and Optimizations for Address Computation in DSP Architectures.

Proceedings of the 9th International Symposium on System Synthesis, 1996

The case for retiming with explicit reset circuitry.

ICCAD, 1996

Using complete-1-distinguishability for FSM equivalence checking.

ICCAD, 1996

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.

Proceedings of the 33st Conference on Design Automation, 1996

1995

Test generation for cyclic combinational circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Functional timing analysis using ATPG.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Exploiting multicycle false paths in the performance optimization of sequential logic circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Multisensor Integration for Underwater Scene Classification.

Appl. Intell., 1995

Test generation for cyclic combinational circuits.

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software.

Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

Performance Analysis of Embedded Software Using Implicit Path Enumeration.

Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, 1995

Power analysis and low-power scheduling techniques for embedded DSP software.

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Optimal code generation for embedded memory non-homogeneous register architectures.

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Guarded evaluation: pushing power management to logic synthesis/design.

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Memory bank and register allocation in software synthesis for ASIPs.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Performance estimation of embedded software with instruction cache modeling.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Fast functional simulation using branching programs.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Prediction of interconnect delay in logic synthesis.

Proceedings of the 1995 European Design and Test Conference, 1995

Performance Analysis of Embedded Software Using Implicit Path Enumeration.

Proceedings of the 32st Conference on Design Automation, 1995

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits.

Proceedings of the 32st Conference on Design Automation, 1995

Limits of using signatures for permutation independent Boolean comparison.

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

Delay abstraction in combinational logic circuits.

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Editorial.

VLSI Signal Processing, 1994

Verification of asynchronous interface circuits with bounded wire delays.

VLSI Signal Processing, 1994

Power analysis of embedded software: a first step towards software power minimization.

IEEE Trans. VLSI Syst., 1994

Certified timing verification and the transition delay of a logic circuit.

IEEE Trans. VLSI Syst., 1994

Analysis of cyclic combinational circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Power analysis of embedded software: a first step towards software power minimization.

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Challenges in code generation for embedded processors.

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Statistical Delay Modeling in Logic Design and Synthesis.

Proceedings of the 31st Conference on Design Automation, 1994

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.

Proceedings of the 31st Conference on Design Automation, 1994

1993

Statistical timing analysis of combinational logic circuits.

IEEE Trans. VLSI Syst., 1993

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Computation of floating mode delay in combinational circuits: practice and implementation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Computation of floating mode delay in combinational circuits: theory and algorithms.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Permutation and phase independent Boolean comparison.

Integration, 1993

A synthesis-based test generation and compaction algorithm for multifaults.

J. Electronic Testing, 1993

Statistical Timing Optimization of Combinatorial Logic Circuits.

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Analysis of cyclic combinational circuits.

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Technology Mapping for Lower Power.

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Symbolic minimization of multilevel logic and the input encoding problem.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Statistical Timing Analysis of Combinational Circuits.

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Verification of asynchronous interface circuits with bounded wire delays.

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Exploiting multi-cycle false paths in the performance optimization of sequential circuits.

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Certified Timing Verification and the Transition Delay of a Logic Circuit.

Proceedings of the 29th Design Automation Conference, 1992

1991

Retiming and resynthesis: optimizing sequential networks with combinational techniques.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Is redundancy necessary to reduce delay?

IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Delay Computation in Combinational Logic Circuits: Theory and Algorithms.

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults.

Proceedings of the 28th Design Automation Conference, 1991

1990

Algorithms for Discrete Function Manipulation.

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Performance Optimization of Pipelined Circuits.

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Is Redundancy Necessary to Reduce Delay.

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988

Logic verification using binary decision diagrams in a logic synthesis environment.

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988