Micaela Serra

Affiliations:
  • University of Victoria, Canada


According to our database1, Micaela Serra authored at least 26 papers between 1987 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2009
ARMSim# - a Customizable Simulator for Exploring the ARM Architecture.
Proceedings of the 2009 International Conference on Frontiers in Education: Computer Science & Computer Engineering, 2009

2007
Codesign of a Computationally Intensive Problem in GF(3).
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

2004
Rapid Prototyping of a Co-Designed Java Virtual Machine.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

2003
Using FPGAs to solve the Hamiltonian cycle problem.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Reconfigurable Architecture Requirements for Co-Designed Virtual Machines.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
The IT Support for Acquired Brain Injury Patients - the Design and Evaluation of a New Software Package.
Proceedings of the 35th Hawaii International Conference on System Sciences (HICSS-35 2002), 2002

Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2000
Fast Algorithms to Generate Necklaces, Unlabeled Necklaces, and Irreducible Polynomials over GF(2).
J. Algorithms, 2000

Hardware/Software Co-Design of a Java Virtual Machine.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Solving Hamiltonian Cycle on FPGA Technology via Instance to Circuit Mappings.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1999
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.
IEEE Trans. Computers, 1999

2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application.
IEEE Trans. Computers, 1999

A Multimedia Virtual Lab for Digital Logic Design.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1998
An Object-Oriented Layered Approach to Interfaces for Hardware/Software Codesign of Embedded Systems.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997
On-line and off-line testing with shared resources: a new BIST approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1995
A new DFT methodology for sequential circuits.
J. Electron. Test., 1995

Sequential logic minimization based on functional testability.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
A Functional Approach to Delay Faults Test Generation for Sequential Circuits.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
State assignment and testability of PLA-based finite state machines.
Microprocess. Microprogramming, 1992

Merging Concurrent Checking and Off-line BIST.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
The analysis of one-dimensional linear cellular automata and their aliasing properties.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

The Analysis of One Dimensional Multiple-Valued Linear Cellular Automata.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1988
Space compaction for multiple-output circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
Testing Programmable Logic Arrays by Sum of Syndromes.
IEEE Trans. Computers, 1987


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