Xicheng Jiang

According to our database1, Xicheng Jiang authored at least 29 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2014, "For development of communication systems-on-chip products".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits, 2016

EE1: Class of 2025 - Where will be the best jobs?
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

F2: Data-converter calibration and dynamic-matching techniques.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Analysis of Current Efficiency for CMOS Class-B LC Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Self-Dithering Technique for High-Resolution SAR ADC Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2015


Session 5 overview: Analog techniques: Analog subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR.
IEEE J. Solid State Circuits, 2014

A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications.
IEEE J. Solid State Circuits, 2014

F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip.
Proceedings of the ESSCIRC 2014, 2014

Configurable incremental sigma-delta ADC for DC measure and audio conversion.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Sub-session: Data converter techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers.
IEEE J. Solid State Circuits, 2013

Analog techniques I.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2012

Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices.
Proceedings of the Symposium on VLSI Circuits, 2012

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Analog Techniques.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator.
IEEE J. Solid State Circuits, 2010

A 10mW stereo audio CODEC in 0.13µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 120dB dynamic range 400mW class-D speaker driver with 4<sup>th</sup>-order PWM modulator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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