Michail Mavropoulos

Orcid: 0000-0003-3289-5315

According to our database1, Michail Mavropoulos authored at least 12 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2022
Enabling efficient sub-block disabled caches using coarse grain spatial predictions.
Microprocess. Microsystems, April, 2022


Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022


2021
A Hierarchical Profiler of Intermediate Representation Code based on LLVM.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021


Run Time Management of Faulty Data Caches.
Proceedings of the 26th IEEE European Test Symposium, 2021

2018
A novel fault tolerant cache architecture based on orthogonal latin squares theory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016
Recovery of performance degradation in defective branch target buffers.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Spatial pattern prediction based management of faulty data caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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