Raphael Weber
Orcid: 0000-0002-2883-4811
According to our database1,
Raphael Weber
authored at least 23 papers
between 2005 and 2023.
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Bibliography
2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the Systems, Software and Services Process Improvement, 2023
2022
XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Towards Automating a Software-Centered Development Process that considers Timing Properties.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2019
Proceedings of the 22nd ACM/IEEE International Conference on Model Driven Engineering Languages and Systems Companion, 2019
2016
Proceedings of the Advanced Model-Based Engineering of Embedded Systems, 2016
Proceedings of the Advanced Model-Based Engineering of Embedded Systems, 2016
Proceedings of the Advanced Model-Based Engineering of Embedded Systems, 2016
2015
Complex Syst. Informatics Model. Q., 2015
Proceedings of the Gemeinsamer Tagungsband der Workshops der Tagung Software Engineering 2015, 2015
A Modular Safety Assurance Method considering Multi-Aspect Contracts during Cyber Physical System Design.
Proceedings of the Joint Proceedings of REFSQ-2015 Workshops, 2015
Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015
2012
Proceedings of the Model-Based Engineering of Embedded Systems, The SPES 2020 Methodology, 2012
2010
A Model-Based Design Methodology with Contracts to Enhance the Development Process of Safety-Critical Systems.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2010
2009
Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture.
Proceedings of the Analysis, 2009
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2007
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
2006
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
2005
Proceedings of the Embedded and Ubiquitous Computing, 2005