Georgios Keramidas

According to our database1, Georgios Keramidas authored at least 37 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management.
ACM Trans. Embedded Comput. Syst., 2018

Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD Displays.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

A novel fault tolerant cache architecture based on orthogonal latin squares theory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Enabling GPU software developers to optimize their applications - The LPGPU2 approach.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Recovery of performance degradation in defective branch target buffers.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Computation and communication challenges to deploy robots in assisted living environments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Revisiting Cache Resizing.
International Journal of Parallel Programming, 2015

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Spatial pattern prediction based management of faulty data caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Performance and power trade-offs for cryptographic applications in embedded processors.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013

2012
A framework for efficient cache resizing.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Embedded reconfigurable architectures.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Poster: DVFS management in real-processors.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Green governors: A framework for Continuously Adaptive DVFS.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
SARC Coherence: Scaling Directory Cache Coherence in Performance and Power.
IEEE Micro, 2010

Interval-based models for run-time DVFS orchestration in superscalar processors.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Where replacement algorithms fail: a thorough analysis.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.
Trans. HiPEAC, 2009

Instruction-based reuse-distance prediction for effective cache management.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008
Non deterministic caches: a simple and effective defense against side channel attacks.
Design Autom. for Emb. Sys., 2008

2007
Cache replacement based on reuse-distance prediction.
Proceedings of the 25th International Conference on Computer Design, 2007

Applying Decay to Reduce Dynamic Power in Set-Associative Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Using value locality to reduce memory encryption overhead in embedded processors.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

2006
Preventing Denial-of-Service Attacks in Shared CMP Caches.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Modeling Cache Sharing on Chip Multiprocessor Architectures.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Dynamic Dictionary-Based Data Compression for Level-1 Caches.
Proceedings of the Architecture of Computing Systems, 2006

2005
A simple mechanism to adapt leakage-control policies to temperature.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

IPStash: a set-associative memory approach for efficient IP-lookup.
Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

2003
IPStash: a Power-Efficient Memory Architecture for IP-lookup.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003


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