Georgios Keramidas

Orcid: 0000-0003-0460-6061

According to our database1, Georgios Keramidas authored at least 85 papers between 2003 and 2024.

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Bibliography

2024
A Practical Approach for Employing Tensor Train Decomposition in Edge Devices.
Int. J. Parallel Program., April, 2024

Introduction to the FPL 2021 Special Section.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

2023
Design and Implementation of Deep Learning 2D Convolutions on Modern CPUs.
IEEE Trans. Parallel Distributed Syst., December, 2023

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application.
Sensors, July, 2023

Efficient OpenCL system integration of non-blocking FPGA accelerators.
Microprocess. Microsystems, March, 2023

Power Efficient Machine Learning Models Deployment on Edge IoT Devices.
Sensors, February, 2023

Towards Highly Compressed CNN Models for Human Activity Recognition in Wearable Devices.
Proceedings of the Signal Processing: Algorithms, 2023

XANDAR: Verification & Validation Approach for Safety-critical Systems.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Gestures detection and device control in AAL environments using machine learning and BLEs.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

A Comparative Study of Neural Network Compilers on ARMv8 Architecture.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022

Enabling efficient sub-block disabled caches using coarse grain spatial predictions.
Microprocess. Microsystems, April, 2022

Design and Implementation of 2D Convolution on x86/x64 Processors.
IEEE Trans. Parallel Distributed Syst., 2022

A Methodology for Efficient Tile Size Selection for Affine Loop Kernels.
Int. J. Parallel Program., 2022


A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Network Simulator as a Service for Demanding Performance Evaluation of Wireless and IoT Scenarios.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2022

An architecture for handling heterogenous services in a speech and language therapy platform.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

Covid-19 protection in AAL environments using thermal and web cameras.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

A Novel Marketplace Perspective Promoting Customized Low Energy Computing and IoT: The SMART4ALL Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022


NS3SaaS: Cloud-based "Network Simulator as a Service" with customisable resource scheduling.
Proceedings of the 11th IEEE International Conference on Cloud Networking, 2022

2021
Challenges Towards Hardware Acceleration of the Deformable Shape Tracking Application.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Social Distance Monitoring using AI techniques in AAL environments.
Proceedings of the IEEE International Conference on Smart Internet of Things, 2021

Comparative evaluation of computer vision technologies, targeting object identification and localization scenarios.
Proceedings of the 6th South-East Europe Design Automation, 2021

Characterization of WiFi Modules Using an Open-Source Network Simulator.
Proceedings of the 6th South-East Europe Design Automation, 2021

An Analytical Model for Loop Tiling Transformation.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Unified OpenCL Integration Methodology for FPGA Designs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

A Hierarchical Profiler of Intermediate Representation Code based on LLVM.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

Smart health monitoring using AI techniques in AAL environments.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

Exploiting Vitis Framework for Accelerating Sobel Algorithm.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

The SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservices.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Architectures for SLAM and Augmented Reality Computing.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021


Run Time Management of Faulty Data Caches.
Proceedings of the 26th IEEE European Test Symposium, 2021

Software Acceleration of the Deformable Shape Tracking Application: How to eliminate the Eigen Library Overhead.
Proceedings of the ESSE 2021: 2nd European Symposium on Software Engineering, Larissa, Greece, November 19, 2021

High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
Guest Editorial Note: Special Issue on Applied Reconfigurable Computing.
J. Signal Process. Syst., 2020

Deep Embedded Vision Using Sparse Convolutional Neural Networks.
ERCIM News, 2020

VLSI for Next Generation CE.
IEEE Consumer Electron. Mag., 2020

Optimizing the Operational Time of Ambient Assisting Living Robots.
IEEE Consumer Electron. Mag., 2020

Toward an ICT-Based Service Oriented Health Care Paradigm.
IEEE Consumer Electron. Mag., 2020

The SMART4ALL toolbox for boosting technology and business development in South, Eastern and Central Europe.
Proceedings of the Signal Processing: Algorithms, 2020

Enhancing Visual Recognition for Door Status Identification in AAL Robots via Machine Learning.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub Perspective.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2018
Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management.
ACM Trans. Embed. Comput. Syst., 2018

Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD Displays.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

A novel fault tolerant cache architecture based on orthogonal latin squares theory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Enabling GPU software developers to optimize their applications - The LPGPU<sup>2</sup> approach.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Recovery of performance degradation in defective branch target buffers.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Computation and communication challenges to deploy robots in assisted living environments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Revisiting Cache Resizing.
Int. J. Parallel Program., 2015

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Spatial pattern prediction based management of faulty data caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Performance and power trade-offs for cryptographic applications in embedded processors.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013

2012
A framework for efficient cache resizing.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Embedded reconfigurable architectures.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Poster: DVFS management in real-processors.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Green governors: A framework for Continuously Adaptive DVFS.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
SARC Coherence: Scaling Directory Cache Coherence in Performance and Power.
IEEE Micro, 2010

Interval-based models for run-time DVFS orchestration in superscalar processors.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Where replacement algorithms fail: a thorough analysis.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.
Trans. High Perform. Embed. Archit. Compil., 2009

Instruction-based reuse-distance prediction for effective cache management.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008
Non deterministic caches: a simple and effective defense against side channel attacks.
Des. Autom. Embed. Syst., 2008

2007
Cache replacement based on reuse-distance prediction.
Proceedings of the 25th International Conference on Computer Design, 2007

Applying Decay to Reduce Dynamic Power in Set-Associative Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Using value locality to reduce memory encryption overhead in embedded processors.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

2006
Preventing Denial-of-Service Attacks in Shared CMP Caches.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Modeling Cache Sharing on Chip Multiprocessor Architectures.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Dynamic Dictionary-Based Data Compression for Level-1 Caches.
Proceedings of the Architecture of Computing Systems, 2006

2005
A simple mechanism to adapt leakage-control policies to temperature.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

IPStash: a set-associative memory approach for efficient IP-lookup.
Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

2003
IPStash: a Power-Efficient Memory Architecture for IP-lookup.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003


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