Michele Rossoni
Orcid: 0009-0005-2684-8549
According to our database1,
Michele Rossoni
authored at least 13 papers
between 2023 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC.
IEEE J. Solid State Circuits, July, 2025
A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC.
IEEE J. Solid State Circuits, June, 2025
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars.
IEEE J. Solid State Circuits, December, 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
IEEE J. Solid State Circuits, December, 2023
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023