Mihailo Isakov

According to our database1, Mihailo Isakov authored at least 31 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Zeno: A Scalable Capability-Based Secure Architecture.
CoRR, 2022

A Taxonomy of Error Sources in HPC I/O Machine Learning Models.
Proceedings of the SC22: International Conference for High Performance Computing, 2022

NeuroFabric: Hardware and ML Model Co-Design for A Priori Sparse Neural Network Training.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

NeuroFabric: Identifying Ideal Topologies for Training A Priori Sparse Networks.
CoRR, 2020

Gauge: An Interactive Data-Driven Visualization Tool for HPC Application I/O Performance Analysis.
Proceedings of the Fifth IEEE/ACM International Parallel Data Systems Workshop, 2020

HPC I/O throughput bottleneck analysis with explainable local models.
Proceedings of the International Conference for High Performance Computing, 2020

Toward Generalizable Models of I/O Throughput.
Proceedings of the 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers, 2020

Homomorphic Encryption Based Secure Sensor Data Processing.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
RASSS: a hijack-resistant confidential information management scheme for distributed systems.
IET Comput. Digit. Tech., 2019

Drndalo: Lightweight Control Flow Obfuscation Through Minimal Processor/Compiler Co-Design.
CoRR, 2019

CodeTrolley: Hardware-Assisted Control Flow Obfuscation.
CoRR, 2019

A secure and robust scheme for sharing confidential information in IoT systems.
Ad Hoc Networks, 2019

The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture.
Proceedings of the Workshop on Computer Architecture Education, 2019

Survey of Attacks and Defenses on Edge-Deployed Neural Networks.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

2018
Designing Secure Heterogeneous Multicore Systems from Untrusted Components.
Cryptogr., 2018

BRISC-V Emulator: A Standalone, Installation-Free, Browser-Based Teaching Tool.
CoRR, 2018

SAPA: Self-Aware Polymorphic Architecture.
CoRR, 2018

ClosNets: a Priori Sparse Topologies for Faster DNN Training.
CoRR, 2018

Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

NoSync: Particle Swarm Inspired Distributed DNN Training.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018

Chameleon: A Generalized Reconfigurable Open-Source Architecture for Deep Neural Network Training.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural Topologies.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.
CoRR, 2017

Adaptive Manycore Architectures for Big Data Computing.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Advertiser elevator: A fault tolerant routing algorithm for partially connected 3D Network-on-Chips.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Janus: An uncertain cache architecture to cope with side channel attacks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Hermes: Secure heterogeneous multicore architecture design.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017


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