Hyoukjun Kwon

Orcid: 0000-0001-9824-1352

According to our database¹, Hyoukjun Kwon authored at least 33 papers between 2017 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

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Other

Bibliography

2023

Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets.

[BibT_eX]

[DOI]

Mohanad Odema

Hyoukjun Kwon

Mohammad Abdullah Al Faruque

CoRR, 2023

DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication.

[BibT_eX]

[DOI]

Sivasankaran Rajamanickam

Tushar Krishna

IEEE Trans. Parallel Distributed Syst., 2022

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2022

A Formalism of DNN Accelerator Flexibility.

[BibT_eX]

[DOI]

Proc. ACM Meas. Anal. Comput. Syst., 2022

SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.

[BibT_eX]

[DOI]

CoRR, 2022

XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.

[BibT_eX]

[DOI]

CoRR, 2022

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021

Flexion: A Quantitative Metric for Flexibility in DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Extending Sparse Tensor Accelerators to Support Multiple Compression Formats.

[BibT_eX]

[DOI]

Sivasankaran Rajamanickam

Tushar Krishna

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Data Orchestration in Deep Learning Accelerators

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01767-4, 2020

Data- and communication-centric approaches to model and design flexible deep neural network accelerators.

[BibT_eX]

[DOI]

Hyoukjun Kwon

PhD thesis, 2020

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.

[BibT_eX]

[DOI]

Venkata Chaitanya Krishna Chekuri

IEEE Trans. Very Large Scale Integr. Syst., 2020

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings.

[BibT_eX]

[DOI]

IEEE Micro, 2020

MARVEL: A Decoupled Model-driven Approach for Efficiently Mapping Convolutions on Spatial DNN Accelerators.

[BibT_eX]

[DOI]

CoRR, 2020

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

HERALD: Optimizing Heterogeneous DNN Accelerators for Edge Devices.

[BibT_eX]

[DOI]

CoRR, 2019

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Understanding the Impact of On-chip Communication on DNN Accelerator Performance.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.

[BibT_eX]

[DOI]

Venkata Chaitanya Krishna Chekuri

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

A Communication-Centric Approach for Designing Flexible DNN Accelerators.

[BibT_eX]

[DOI]

Hyoukjun Kwon

Ananda Samajdar

Tushar Krishna

IEEE Micro, 2018

MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators.

[BibT_eX]

[DOI]

Hyoukjun Kwon

Michael Pellauer

Tushar Krishna

CoRR, 2018

Architecting a Secure Wireless Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2018

MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.

[BibT_eX]

[DOI]

Hyoukjun Kwon

Ananda Samajdar

Tushar Krishna

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

Rethinking NoCs for Spatial Neural Network Accelerators.

[BibT_eX]

[DOI]

Hyoukjun Kwon

Ananda Samajdar

Tushar Krishna

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Adaptive Manycore Architectures for Big Data Computing.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel.

[BibT_eX]

[DOI]

Hyoukjun Kwon

Tushar Krishna

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants.

[BibT_eX]

[DOI]

Hyoukjun Kwon

William Harris

Hadi Esmaeilzadeh

Proceedings of the 30th IEEE Computer Security Foundations Symposium, 2017

Hyoukjun Kwon

Timeline

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