Tushar Krishna

According to our database1, Tushar Krishna authored at least 61 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
CoRR, 2020

2019
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom.
IEEE Micro, 2019

HERALD: Optimizing Heterogeneous DNN Accelerators for Edge Devices.
CoRR, 2019

BINDU: deadlock-freedom with one bubble in the network.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Reinforcement learning based interconnection routing for adaptive traffic optimization.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A communication-centric approach for designing flexible DNN accelerators.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Understanding the Impact of On-chip Communication on DNN Accelerator Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Communication-Centric Approach for Designing Flexible DNN Accelerators.
IEEE Micro, 2018

SCALE-Sim: Systolic CNN Accelerator.
CoRR, 2018

MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators.
CoRR, 2018

Brownian Bubble Router: Enabling Deadlock Freedom via Guaranteed Forward Progress.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Architecting a Secure Wireless Network-on-Chip.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

SEESAW: Using Superpages to Improve VIPT Caches.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip.
Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2018

FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Optimizing the data placement and transformation for multi-bank CGRA computing system.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

LATR: Lazy Translation Coherence.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
On-Chip Networks, Second Edition
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2017

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks.
J. Solid-State Circuits, 2017

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.
CoRR, 2017

VESPA: VIPT Enhancements for Superpage Accesses.
CoRR, 2017

Rethinking NoCs for Spatial Neural Network Accelerators.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Adaptive Manycore Architectures for Big Data Computing.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Lightweight Emulation of Virtual Channels using Swaps.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017

OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Static Bubble: A Framework for Deadlock-Free Irregular On-chip Topologies.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.
ACM Trans. Comput. Syst., 2015

2014
Enabling dedicated single-cycle connections over a shared network-on-chip.
PhD thesis, 2014

Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip.
IEEE Micro, 2014

Single-cycle collective communication over a shared network fabric.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects.
IEEE Trans. VLSI Syst., 2013

Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks.
IEEE Computer, 2013

Breaking the on-chip latency barrier using SMART.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

SMART: a single-cycle reconfigurable NoC for SoC applications.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
The gem5 simulator.
SIGARCH Computer Architecture News, 2011

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

A low-swing crossbar and link generator for low-power networks-on-chip.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.
Proceedings of the NOCS 2010, 2010

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Express Virtual Channels with Capacitively Driven Global Links.
IEEE Micro, 2009

GARNET: A detailed on-chip network model inside a full-system simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2008
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008


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