Pengju Ren

According to our database1, Pengju Ren authored at least 46 papers between 2008 and 2021.

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Bibliography

2021
Linear and Nonlinear Regression-Based Maximum Correntropy Extended Kalman Filtering.
IEEE Trans. Syst. Man Cybern. Syst., 2021

PIT: Processing-In-Transmission With Fine-Grained Data Manipulation Networks.
IEEE Trans. Computers, 2021

Error Loss Networks.
CoRR, 2021

GroupifyVAE: from Group-based Definition to VAE-based Unsupervised Representation Disentanglement.
CoRR, 2021

A Lightweight sequence-based Unsupervised Loop Closure Detection.
Proceedings of the International Joint Conference on Neural Networks, 2021

Joint Critics Mechanism: A Universal Framework for Multi-targets Visual Navigation.
Proceedings of the International Joint Conference on Neural Networks, 2021

CAQ: Context-Aware Quantization via Reinforcement Learning.
Proceedings of the International Joint Conference on Neural Networks, 2021

SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Robust Power System State Estimation With Minimum Error Entropy Unscented Kalman Filter.
IEEE Trans. Instrum. Meas., 2020

A 4K × 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

EMG-Based Gestures Classification Using a Mixed-Signal Neuromorphic Processing System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Visual Semantic SLAM with Landmarks for Large-Scale Outdoor Environment.
CoRR, 2020

Exploring Better Speculation and Data Locality in Sparse Matrix-Vector Multiplication on Intel Xeon.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

CentripetalNet: Pursuing High-Quality Keypoint Pairs for Object Detection.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Neuromorphic Implementation of a Recurrent Neural Network for EMG Classification.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Maximum Total Correntropy Diffusion Adaptation Over Networks With Noisy Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Design Space Exploration of Neural Network Activation Function Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Asymmetric Correntropy for Robust Adaptive Filtering.
CoRR, 2019

Multi-Kernel Correntropy for Robust Learning.
CoRR, 2019

2018
Reconstruction of Visual Image From Functional Magnetic Resonance Imaging Using Spiking Neuron Model.
IEEE Trans. Cogn. Dev. Syst., 2018

A novel spiking neural network of receptive field encoding with groups of neurons decision.
Frontiers Inf. Technol. Electron. Eng., 2018

Spiking Locality-Sensitive Hash: Spiking Computation with Phase Encoding Method.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Multitask Learning With Enhanced Modules.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Activations Quantization for Compact Neural Networks.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Toward an Efficient Multiview Display Processing Architecture for 3DTV.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Hybrid-augmented intelligence: collaboration and cognition.
Frontiers Inf. Technol. Electron. Eng., 2017

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.
CoRR, 2017

2016
A Deadlock-Free and Connectivity-Guaranteed Methodology for Achieving Fault-Tolerance in On-Chip Networks.
IEEE Trans. Computers, 2016

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies.
IEEE Trans. Computers, 2016

A reconfigurable parallel FPGA accelerator for the adapt-then-combine diffusion LMS algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Towards connectivity-guaranteed power-gating large-scale on-chip networks.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
A reconfigurable parallel FPGA accelerator for the kernel affine projection algorithm.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

A high efficient hardware architecture for multiview 3DTV.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A real-time permutation entropy computation for EEG signals.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A 128-way FPGA platform for the acceleration of KLMS algorithm.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Hardware implementation of KLMS algorithm using FPGA.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

A reconfigurable parallel acceleration platform for evaluation of permutation entropy.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Fault-tolerant Routing for On-chip Network Without Using Virtual Channels.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A high-throughput fixed-point complex divider for FPGAs.
IEICE Electron. Express, 2013

Depth map generation from geometry and motion.
Proceedings of the Fifth International Conference on Digital Image Processing, 2013

2012
HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.
Microprocess. Microsystems, 2011

Scalable, accurate multicore simulation in the 1000-core era.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

2008
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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