Ming-Long Fan

According to our database1, Ming-Long Fan authored at least 21 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2015
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation.
Microelectron. Reliab., 2015

Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab., 2014

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Analysis of power-performance for ultra-thin-body GeOI logic circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2009
Design and analysis of ultra-thin-body SOI based subthreshold SRAM.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009


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