Jen-Huan Tsai

According to our database1, Jen-Huan Tsai authored at least 8 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015
A 0.003 mm<sup>2</sup> 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.
IEEE J. Solid State Circuits, 2015

A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics.
IEEE J. Solid State Circuits, 2015

2014
A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC.
IEEE Trans. Circuits Syst. II Express Briefs, 2010


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