Yin-Nien Chen
Affiliations:- National Chiao Tung University, Hsinchu City, Taiwan
According to our database1,
Yin-Nien Chen
authored at least 17 papers
between 2011 and 2017.
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Bibliography
2017
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling.
Proceedings of the International Conference on IC Design and Technology, 2016
2015
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab., 2014
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011