Minghua Shen

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

Improving the exploration efficiency of DQNs via the confidence bound methods.

[BibT_eX]

[DOI]

Appl. Intell., 2022

Exploiting data locality in memory for ORAM to reduce memory access overheads.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Coarse-Grained Parallel Routing With Recursive Partitioning for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

Model Parallelism Optimization for Distributed Inference Via Decoupled CNN Structure.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Krill: a compiler and runtime system for concurrent graph processing.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2021

Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

A Practical High-Level Synthesis Framework.

[BibT_eX]

[DOI]

Aoxiang Qin

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

EEPC: A Framework for Energy-Efficient Parallel Control of Connected Cars.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Serial-Equivalent Static and Dynamic Parallel Routing for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Entropy-Directed Scheduling for FPGA High-Level Synthesis.

[BibT_eX]

[DOI]

Hongzheng Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Distributed In-Situ CNN Inference System for IoT Applications.

[BibT_eX]

[DOI]

Jiangsu Du

Yunfei Du

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Exploring GPU-Accelerated Routing for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2019

A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS.

[BibT_eX]

[DOI]

Hongzheng Chen

Proceedings of the International Conference on Computer-Aided Design, 2019

Parrot: A More Effective Parallel Routing Approach to FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis.

[BibT_eX]

[DOI]

Hongzheng Chen

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Raparo: Resource-Level Angle-Based Parallel Routing for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Fine-Grained Parallel Routing for FPGAs with Selective Expansion.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

DP-Pack: Distributed Parallel Packing for FPGAs.

[BibT_eX]

[DOI]

Qiangpu Chen

Proceedings of the International Conference on Field-Programmable Technology, 2018

Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Tiguan: Energy-aware collision-free control for large-scale connected vehicles.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Dependency-Aware Parallel Routing for Large-Scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A coordinated synchronous and asynchronous parallel routing approach for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Megrez: Parallelizing FPGA Routing with Strictly-Ordered Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2015

Accelerate FPGA Routing with Parallel Recursive Partitioning.

[BibT_eX]

[DOI]