Jiaxi Zhang

Orcid: 0000-0001-6599-6142

Affiliations:
  • Peking University, Beijing, China


According to our database1, Jiaxi Zhang authored at least 24 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
PowerSyn: A Logic Synthesis Framework With Early Power Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA.
CoRR, 2023

Automated Design of Chiplets.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Fast Exact NPN Classification with Influence-Aided Canonical Form.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper).
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Dual-Output LUT Merging during FPGA Technology Mapping.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Frequency Improvement of Systolic Array-Based CNNs on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Adaptive-precision framework for SGD using deep Q-learning.
Proceedings of the International Conference on Computer-Aided Design, 2018

Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Search space reduction for the non-exact projective NPNP Boolean matching problem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Scaling Up Physical Design: Challenges and Opportunities.
Proceedings of the 2016 on International Symposium on Physical Design, 2016


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