Mingyu Wang
Orcid: 0000-0003-4006-8870Affiliations:
- Sun Yat-sen University, School of Microelectronics Science and Technology, Guangzhou, China
According to our database1,
Mingyu Wang
authored at least 15 papers
between 2017 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
2024
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2017
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017