Minyi Lu

Orcid: 0000-0001-7227-3735

According to our database1, Minyi Lu authored at least 10 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Sports training simulation system based on video processing technology.
Proceedings of the ICISCAE 2021: 4th International Conference on Information Systems and Computer Aided Education, Dalian, China, September 24, 2021

2020
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.
IEEE Trans. Circuits Syst., 2020

Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits, 2020

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020

2018
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access, 2018

Differential Power Analysis of 8-Bit Datapath AES for IoT Applications.
Proceedings of the 17th IEEE International Conference On Trust, 2018

A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS.
Proceedings of the 17th IEEE International Conference On Trust, 2018

Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES.
Proceedings of the 17th IEEE International Conference On Trust, 2018

A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
An improved timing error prediction monitor for wide adaptive frequency scaling.
IEICE Electron. Express, 2017


  Loading...