Xinning Liu

According to our database1, Xinning Liu authored at least 19 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl., 2019

A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM.
IEEE J. Solid State Circuits, 2018

Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures.
J. Circuits Syst. Comput., 2018

A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
An improved timing error prediction monitor for wide adaptive frequency scaling.
IEICE Electron. Express, 2017

Analytical inverter chain's delay and its variation model for sub-threshold circuits.
IEICE Electron. Express, 2017

Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
A GPS Bit Synchronization Method Based on Frequency Compensation.
IEICE Trans. Commun., 2015

2012
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012

An energy-efficiency Optimized LEACH-C for wireless sensor networks.
Proceedings of the 7th International Conference on Communications and Networking in China, 2012


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