Zhikuang Cai

Orcid: 0000-0002-0264-3849

According to our database1, Zhikuang Cai authored at least 43 papers between 2009 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A low-power self-reference Class-C VCO with dual feedback loops.
Microelectron. J., 2026

A highly robust shallow snapback dual direction SCR for industry-level RS485 on-chip ESD protection.
Microelectron. J., 2026

A sensing-memory-computing integrated optoelectronic synaptic device based on Ag/PtTe2/FTO for artificial vision information processing.
Sci. China Inf. Sci., 2026

A Compact Wide-Band RF Energy Harvesting Front-End Based on an On-Chip IMN with 51.78% Peak PCE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 8-19-GHz Current-Reused Wideband LNA With Dual Transformer Feedback.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
An Effective Faults Detection Method for RRAM Application.
IEEE Trans. Very Large Scale Integr. Syst., December, 2025

A Path Statistical Delay Prediction Framework Based on Global Graph Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025

A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2025

Clean Code In Practice: Challenges and Opportunities.
CoRR, July, 2025

Fully Depleted Silicon-On-Insulator MOSFET pH Sensor With n/p-Si Junction Channel Induced Super-Nernstian Sensitivity and Low Power.
IEEE Trans. Instrum. Meas., 2025

Test and Diagnosis Strategies for Interchiplet Interconnects.
IEEE Trans. Instrum. Meas., 2025

Post-Routing Path Statistical Delay Estimation Based on SGAT-GRU Prediction Framework.
Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

Mismatch Analysis of DDCC Rectifier for 2.4GHz-band high-sensitive RF Energy Harvesting System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
A 16-MHz Crystal Oscillator With 17.5- μ s Start-Up Time Under 10<sup>4</sup>-ppm- Δ F Injection Using Automatic Phase-Error Correction.
IEEE J. Solid State Circuits, November, 2024

A CMOS Current Sensing Interface With Sub-pA DC Uncertainty.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

Design of memristor-based combinational logic circuits.
IEICE Electron. Express, 2024

2023
A 16MHz X0 with 17.5μs Startup Time Under 10<sup>4</sup>ppm-ΔF Injection Using Automatic Phase-Error Correction Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS.
IEICE Electron. Express, 2021

An optimized DFT technology based on machine learning.
Proceedings of the IEEE International Test Conference in Asia, 2021

2020
Design of a compact chip filter with two transmission zeros using 0.35 μm GaAs HBT.
Microelectron. J., 2020

A low-power 2.4-GHz receiver front-end with a complementary series feedback LNA and a current-reused passive down-converter based on gm-boosted TIA for WSN applications.
IEICE Electron. Express, 2020

An effective technique preventing differential cryptanalysis attack.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
A 2.4 GHz 2.2 mW current reusing passive mixer with gm-boosted common-gate TIA in 180 nm CMOS.
IEICE Electron. Express, 2019

A Novel BIST Algorithm for Low-Voltage SRAM.
Proceedings of the IEEE International Test Conference in Asia, 2019

Design of Low-Cost Ground Penetrating Radar Receiving Circuit Based on Equivalent Sampling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement.
IEICE Electron. Express, 2018

An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO.
IEICE Electron. Express, 2018

A 0.2-6 GHz linearized Darlington-cascode broadband power amplifier.
IEICE Electron. Express, 2018

An improved BIJM circuit based on undersampling technique.
IEICE Electron. Express, 2018

A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique.
IEICE Electron. Express, 2018

2017
A 2.4-GHz all-digital phase-locked loop with a pipeline-ΔΣ time-to-digital converter.
IEICE Electron. Express, 2017

An improved timing error prediction monitor for wide adaptive frequency scaling.
IEICE Electron. Express, 2017

Built-in jitter measurement circuit for PLL based on variable vernier delay line.
IEICE Electron. Express, 2017

A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
A wide-range and fast-locking all digital SARDLL for DVFS SoCs.
IEICE Electron. Express, 2015

A 0.6 V passive mixer with high conversion gain in 65 nm CMOS process.
IEICE Electron. Express, 2015

2014
A low-cost built-in self-test for CP-PLL based on TDC.
IEICE Electron. Express, 2014

Quasar signal estimation and compensation for data processing in VLBI receiver.
IEICE Electron. Express, 2014

2013
A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking.
IEICE Electron. Express, 2013

On-chip long-term jitter measurement for PLL based on undersampling technique.
IEICE Electron. Express, 2013

2012
An optimized QFP structure for use in radio frequency multi-chip module applications.
IEICE Electron. Express, 2012

2009
A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme.
IEICE Trans. Electron., 2009


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