Longxing Shi
Orcid: 0000-0002-0629-7154
According to our database1,
Longxing Shi
authored at least 127 papers
between 2000 and 2024.
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Bibliography
2024
VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Ind. Electron., November, 2023
Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation.
Integr., November, 2023
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
CharTM: The dynamic stability characterization for memory based on tail distribution modeling.
Microelectron. J., March, 2023
An efficient SRAM yield analysis method based on scaled-sigma adaptive importance sampling with meta-model accelerated.
Integr., March, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
An Analytical Model for Domain-Specific Accelerator Deploying Sparse LU Factorization.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation.
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.
CoRR, 2022
2021
A Novel Digital Control Method of Primary-Side Regulated Flyback With Active Clamping Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
Design and implementation of a hybrid DPWM under 50 ps resolution based on general-purpose FPGA.
Int. J. Circuit Theory Appl., 2021
The Effect of High Temperature Ion Implantation on the Performance of 1.2kV 4H-SiC MOSFETs.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits, 2020
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020
IEEE Embed. Syst. Lett., 2020
VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models.
IEEE Access, 2020
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl., 2019
An energy-efficient voice activity detector using deep neural networks and approximate computing.
Microelectron. J., 2019
ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs.
Microelectron. J., 2019
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocess. Microsystems, 2019
EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing.
IEEE Access, 2019
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis.
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
An Accurate and Efficient Yield Analysis for SRAM dynamic metrics Using Differential Evolution Algorithm.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Noise Immunity and its Temperature Characteristics Study of the Capacitive-Loaded Level Shift Circuit for High Voltage Gate Drive IC.
IEEE Trans. Ind. Electron., 2018
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embed. Comput. Syst., 2018
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network.
Sensors, 2018
A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM.
IEEE J. Solid State Circuits, 2018
J. Syst. Archit., 2018
EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing.
IEEE Access, 2018
IEEE Access, 2018
Proceedings of the 24th International Conference on Pattern Recognition, 2018
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems, 2017
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocess. Microsystems, 2017
E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing.
IEICE Electron. Express, 2017
In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications.
IEEE Access, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
A trace-driven analytical model with less profiling overhead for DRAM access latencies.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Trajectory prediction control for digital control DC-DC converters with fast transient response.
Microelectron. J., 2014
A method for estimating the 3D rendering performance of the SoC in the early design stage.
IEICE Electron. Express, 2014
An energy efficient OpenCL implementation of a fingerprint verification system on heterogeneous mobile device.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor.
IEEE Trans. Signal Process., 2013
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware.
IEEE Trans. Instrum. Meas., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip.
IEICE Trans. Inf. Syst., 2013
IEICE Trans. Inf. Syst., 2013
Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC.
IEICE Trans. Inf. Syst., 2013
IEICE Electron. Express, 2013
IEICE Electron. Express, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture.
IEICE Trans. Inf. Syst., 2012
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
IEICE Trans. Commun., 2012
An optimized QFP structure for use in radio frequency multi-chip module applications.
IEICE Electron. Express, 2012
2011
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Microelectron. J., 2011
An 11.2-mW 5-GHz CMOS Frequency Synthesizer with Low Power Prescaler for Zigbee Application.
IEICE Trans. Electron., 2011
IEICE Electron. Express, 2011
Proceedings of the 7th International Wireless Communications and Mobile Computing Conference, 2011
A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme.
J. Signal Process. Syst., 2010
Devices' optimization against hot-carrier degradation in high voltage pLEDMOS transistor.
Microelectron. Reliab., 2010
Investigation of the shift of hot spot in lateral diffused LDMOS under ESD conditions.
Microelectron. Reliab., 2010
An adaptive energy-efficient and low-latency MAC protocol for wireless sensor networks.
J. Commun. Networks, 2010
A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2009
Low cost bulk-silicon CDMOS technology and enhanced dv/dt high voltage driver circuit for PDP data driver IC.
Microelectron. J., 2009
Extended Control Flow Graph Based Performance and Energy Consumption Optimization Using Scratch-Pad Memory.
J. Circuits Syst. Comput., 2009
Temperature-stable voltage reference based on different threshold voltages of NMOS transistors.
IET Circuits Devices Syst., 2009
IEICE Trans. Commun., 2009
Integrated Current Sensing Technique Suitable for Step-Down Switch-Mode Power Converters.
IEICE Trans. Electron., 2009
A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme.
IEICE Trans. Electron., 2009
Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
2008
Microelectron. Reliab., 2008
Bulk-silicon power integrated circuit technology for 192-channel data driver ICs of plasma display panel.
IET Circuits Devices Syst., 2008
IEICE Trans. Electron., 2008
On the use of multi-tone for the measurement of noise power ratio distortion in RF circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007
2006
Microelectron. Reliab., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Microelectron. Reliab., 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2000
A 900-MHz fully integrated SOI power amplifier for single-chip wireless transceiver applications.
IEEE J. Solid State Circuits, 2000