Mithlesh Shrivas

According to our database, Mithlesh Shrivas authored at least 4 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS.

Johan Nguyen, Khaled Khalaf, Xinyan Tang, Steven Brebels, Kristof Vaesen, Mithlesh Shrivas, Piet Wambacq

IEEE J. Solid State Circuits, 2023

2022

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.

Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx

IEEE J. Solid State Circuits, 2022

2021

A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW.

Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.

Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021