Benjamin P. Hershberg
Orcid: 0000-0003-3688-2589
According to our database1,
Benjamin P. Hershberg
authored at least 38 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration.
IEEE J. Solid State Circuits, March, 2024
2023
A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.
IEEE J. Solid State Circuits, 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization.
IEEE J. Solid State Circuits, 2018
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the IEEE International Symposium on Dynamic Spectrum Access Networks, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction.
Proceedings of the ESSCIRC 2014, 2014
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
The effect of correlated level shifting on noise performance in switched capacitor circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Binary Access Memory: An optimized lookup table for successive approximation applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp.
IEEE J. Solid State Circuits, 2010
A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009