Jan Craninckx
Orcid: 0000-0002-3980-0203Affiliations:
- imec, Leuven, Belgium
According to our database1,
Jan Craninckx
authored at least 171 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For contributions to the design of CMOS RF transceivers".
Timeline
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Online presence:
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on scopus.com
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on orcid.org
On csauthors.net:
Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout.
IEEE J. Solid State Circuits, 2023
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE J. Solid State Circuits, 2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.
IEEE J. Solid State Circuits, 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4<sup>th</sup> Nyquist Zone in 1GS/s ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication.
IEEE J. Solid State Circuits, 2020
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
IEEE J. Solid State Circuits, 2020
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 1<sup>st</sup> Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
2019
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels.
IEEE Trans. Biomed. Circuits Syst., 2019
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth.
IEEE J. Solid State Circuits, 2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Sensors, 2018
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA.
IEEE J. Solid State Circuits, 2018
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization.
IEEE J. Solid State Circuits, 2018
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers.
J. Signal Process. Syst., 2015
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation.
IEEE J. Solid State Circuits, 2015
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter.
IEEE J. Solid State Circuits, 2015
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range".
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5<sup>th</sup>-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power.
Proceedings of the ESSCIRC Conference 2015, 2015
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range.
IEEE J. Solid State Circuits, 2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014
IEEE J. Sel. Areas Commun., 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the ESSCIRC 2014, 2014
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the ESSCIRC 2014, 2014
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3.
Proceedings of the ESSCIRC 2014, 2014
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014
A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation.
Proceedings of the 1st International Conference on 5G for Ubiquitous Connectivity, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited).
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2012
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.
IEEE J. Solid State Circuits, 2012
IEEE Commun. Mag., 2012
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Design of an intrinsically-linear double-VCO-based ADC with 2<sup>nd</sup>-order noise shaping.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the Bio-Medical CMOS ICs, 2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
A 0.5 mm <sup>2</sup> Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler.
IEEE J. Solid State Circuits, 2010
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Green Software Defined Radios - Enabling seamless connectivity while saving on hardware and energy
Series on Integrated Circuits and Systems, Springer, ISBN: 978-1-4020-8212-2, 2009
IEEE J. Sel. Top. Signal Process., 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G<sub>m</sub>-C Biquad in 0.13-mu m CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer.
IEEE J. Solid State Circuits, 2008
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A Single-Inductor Dual-Band VCO in a 0.06mm<sup>2</sup> 5.6GHz Multi-Band Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of IEEE International Conference on Communications, 2008
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008
2007
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.
IEEE J. Solid State Circuits, 2007
Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Proceedings of the 40th Design Automation Conference, 2003
1998
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, December, 1995
IEEE J. Solid State Circuits, July, 1995