Ewout Martens
Orcid: 0000-0001-5485-1837
According to our database1,
Ewout Martens
authored at least 53 papers
between 2002 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.
IEEE J. Solid State Circuits, 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4<sup>th</sup> Nyquist Zone in 1GS/s ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels.
IEEE Trans. Biomed. Circuits Syst., 2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization.
IEEE J. Solid State Circuits, 2018
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation.
IEEE J. Solid State Circuits, 2015
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5<sup>th</sup>-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.
IEEE J. Solid State Circuits, 2012
2009
Integr., 2009
2008
Classification of analog synthesis tools based on their architecture selection mechanisms.
Integr., 2008
2007
High-level modeling and synthesis of analog integrated systems ; Hoog-niveau synthese van analoge geïntegreerde systemen.
PhD thesis, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Forum on specification and Design Languages, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series.
Proceedings of the 2005 Design, 2005
2004
An analytical integration method for the simulation of continuous-time ΔΣ modulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design.
Proceedings of the 2004 Design, 2004
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Proceedings of the 2003 Design, 2003
2002
Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 Design, 2002