Jorge Luis Lagos-Benites
Orcid: 0000-0001-5682-8737Affiliations:
- imec, Leuven, Belgium
- Polytechnic University of Turin, Italy (2006 - 2011)
According to our database1,
Jorge Luis Lagos-Benites
authored at least 26 papers
between 2007 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.
IEEE J. Solid State Circuits, 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4<sup>th</sup> Nyquist Zone in 1GS/s ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Proceedings of the 16th European Test Symposium, 2011
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2007
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007