Piet Wambacq
Orcid: 0000-0003-4388-7257Affiliations:
- Vrije Universiteit Brussel
According to our database1,
Piet Wambacq
authored at least 193 papers
between 1991 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE J. Solid State Circuits, 2023
Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout.
IEEE J. Solid State Circuits, 2023
A 0.13μm GaAs HEMT Reconfigurable Balance-to-Doherty Stacked Power Amplifier for 5G mm-wave Applications.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-End in 0.15μm GaN-on-SiC Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023
2022
IEEE J. Solid State Circuits, 2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS.
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Low 1/f<sup>3</sup> Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication.
IEEE J. Solid State Circuits, 2020
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
IEEE J. Solid State Circuits, 2020
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 1<sup>st</sup> Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 22-29 GHz Voltage-Biased LC-VCO with Suppressed Flicker Noise over Tuning Range in 22nm FD-SOI.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Design of A D-band Transformer-Based Neutralized Class-AB Power Amplifier in Silicon Technologies.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Sensors, 2018
A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars.
IEEE J. Solid State Circuits, 2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication.
IEEE J. Solid State Circuits, 2016
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Lecture Notes in Electrical Engineering 346, Springer, ISBN: 978-3-662-46938-5, 2015
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers.
J. Signal Process. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE J. Solid State Circuits, 2015
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range".
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
19.7 A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5<sup>th</sup>-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power.
Proceedings of the ESSCIRC Conference 2015, 2015
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection.
Proceedings of the ESSCIRC Conference 2015, 2015
A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the ESSCIRC 2014, 2014
A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the ESSCIRC 2014, 2014
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited).
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Microelectron. Reliab., 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G<sub>m</sub>-C Biquad in 0.13-mu m CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A Single-Inductor Dual-Band VCO in a 0.06mm<sup>2</sup> 5.6GHz Multi-Band Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE J. Solid State Circuits, 2007
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications.
Proceedings of IEEE International Conference on Communications, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate.
IEEE J. Solid State Circuits, 2006
IEEE J. Sel. Areas Commun., 2006
EURASIP J. Wirel. Commun. Netw., 2006
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of IEEE International Conference on Communications, 2006
Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Microelectron. Reliab., 2005
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors.
IEEE J. Solid State Circuits, 2005
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.
Proceedings of the 2005 Design, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
IEEE J. Solid State Circuits, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Proceedings of the 2004 Design, 2004
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004
A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the ESSCIRC 2003, 2003
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
Proceedings of the ESSCIRC 2003, 2003
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
2002
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions.
Proceedings of the 2002 Design, 2002
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach .
Proceedings of the 2002 Design, 2002
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Analysis and experimental verification of digital substrate noise generation for epi-type substrates.
IEEE J. Solid State Circuits, 2000
Proceedings of the 2000 Design, 2000
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers.
Proceedings of the 37th Conference on Design Automation, 2000
1999
High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 1999 Design, 1999
1995
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits.
IEEE J. Solid State Circuits, March, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Proc. IEEE, 1994
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1991
Proceedings of the conference on European design automation, 1991