Mitsuru Shiozaki

According to our database, Mitsuru Shiozaki authored at least 29 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version.

Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

2021

Deep learning side-channel attack against hardware implementations of AES.

Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino

Microprocess. Microsystems, November, 2021

Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF.

Mitsuru Shiozaki, Takeshi Fujino

J. Cryptogr. Eng., 2021

Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis.

Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

2020

Entropy Estimation of Physically Unclonable Functions.

Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino

IACR Cryptol. ePrint Arch., 2020

Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator.

Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Cause Analysis Method of Entropy Loss in Physically Unclonable Functions.

Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploring Effect of Residual Electric Charges on Cryptographic Circuits.

Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2019

Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis.

Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF.

Mitsuru Shiozaki, Takeshi Fujino

Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018

A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF.

Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2017

Tamper-resistant cryptographic hardware.

Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki

IEICE Electron. Express, 2017

Malicious CAN-message attack against advanced driving assistant system.

Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2015

Reversing stealthy dopant-level circuits.

Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino

J. Cryptogr. Eng., 2015

Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM.

Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

On measurable side-channel leaks inside ASIC design primitives.

Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino

J. Cryptogr. Eng., 2014

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks.

Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.

Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Diffusion Programmable Device : The device to prevent reverse engineering.

Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino

IACR Cryptol. ePrint Arch., 2014

Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks.

Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications.

Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2012

High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.

Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Electron., 2012

Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit.

Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement.

Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL.

Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino

Proceedings of the HOST 2011, 2011

2007

12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique.

Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

20GHz uniform-phase uniform-amplitude standing-wave clock distribution.

Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda

IEICE Electron. Express, 2006

2005

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors.

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata

J. Robotics Mechatronics, 2005

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique.

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata

IEICE Trans. Electron., 2005