Yohei Hori
Orcid: 0000-0003-0099-6090
According to our database1,
Yohei Hori
authored at least 28 papers
between 2000 and 2021.
Collaborative distances:
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Bibliography
2021
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices.
IEICE Trans. Commun., 2021
2020
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr., 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2019
DeviceVeil: Robust Authentication for Individual USB Devices Using Physical Unclonable Functions.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
2018
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.
IEICE Trans. Inf. Syst., 2018
Development of the Unified Security Requirements of PUFs During the Standardization Process.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2018
2017
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
2016
Implementation of pseudo linear feedback shift register physical unclonable function on silicon.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
2014
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays.
J. Inf. Process., 2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
2013
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption.
IEICE Trans. Inf. Syst., 2013
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
Proceedings of the HOST 2011, 2011
2010
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
2008
IEICE Trans. Inf. Syst., 2008
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems.
Proceedings of the Advances in Information and Computer Security, 2008
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems.
Proceedings of the FPL 2008, 2008
2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
2006
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2004
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
2002
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002
2000
Proceedings of the Computers and Games, Second International Conference, 2000